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參數(shù)資料
| 型號(hào)： | S3033 |
| 廠商： | APPLIEDMICRO INC |
| 元件分類： | 數(shù)字傳輸電路 |
| 英文描述： | SONET/SDH/ATM OC-3/12 Transceiver(帶片上高頻鎖相環(huán)的SONET/SDH收發(fā)器（完全集成OC-3/12接口器件）) |
| 中文描述： | TRANSCEIVER, PQFP64 |
| 封裝： | 10 X 10 MM, PLASTIC, QFP-64 |
| 文件頁(yè)數(shù)： | 3/20頁(yè) |
| 文件大?。?/td> | 154K |
| 代理商： | S3033 |
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S3033
SONET/SDH/ATM OC-3/OC-12 TRANSCEIVER
April 7, 2000 / Revision D
S3033 OVERVIEW
The S3033 transceiver implements SONET/SDH se-
rialization/deserialization, transmission, and frame
detection/recovery functions. The block diagram in
Figure 4 shows the basic operation of the chip. This
chip can be used to implement the front end of
SONET equipment, which consists primarily of the
serial transmit interface and the serial receive inter-
face. The chip handles all the functions of these two
elements, including parallel-to-serial and serial-to-par-
allel conversion, clock generation, and system
timing. The system timing circuitry consists of man-
agement of the data stream, framing, and clock
distribution throughout the front end.
The S3033 is divided into a transmitter section and a
receiver section. The sequence of operations is as
follows:
Transmitter Operations:
1. 8-bit parallel input
2. Parallel-to-serial conversion
3. Serial output
Receiver Operations:
1. Frame detection
2. Serial-to-parallel conversion
3. 8-bit parallel output
Internal clocking and control functions are transpar-
ent to the user. Details of data timing can be seen in
Figures 7 through 10.
Figure 4. S3033 Transceiver Functional Block Diagram
1:8 SERIAL
TO PARALLEL
TIMING
GEN
M
U
X
DECISION
CKT
RSDP/N
FRAME
BYTE
DETECT
DLEB
OOF
FP
POUT[7:0]
8
SDTTL
SDPECL
POCLK
8
PIN[7:0]
8:1 PARALLEL
TO SERIAL
TSDP/N
PICLK
TIMING
GEN
PCLK
19MHZCLK
CLOCK
SYNTHESIZER
RSTB
D
TSTRST
MODE0
MODE1
CAP1
CAP2
Transmitter
Receiver
TSCLKP/N
LLEB
SLPTIME
REFCLKP/N
TTLREF
RLPTIME
TSCLKP/N
RSCLKP/N
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