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參數(shù)資料
| 型號： | S3033 |
| 廠商： | APPLIEDMICRO INC |
| 元件分類： | 數(shù)字傳輸電路 |
| 英文描述： | SONET/SDH/ATM OC-3/12 Transceiver(帶片上高頻鎖相環(huán)的SONET/SDH收發(fā)器（完全集成OC-3/12接口器件）) |
| 中文描述： | TRANSCEIVER, PQFP64 |
| 封裝： | 10 X 10 MM, PLASTIC, QFP-64 |
| 文件頁數(shù)： | 5/20頁 |
| 文件大?。?/td> | 154K |
| 代理商： | S3033 |
5
S3033
SONET/SDH/ATM OC-3/OC-12 TRANSCEIVER
April 7, 2000 / Revision D
RECEIVER OPERATION
The S3033 transceiver chip provides the first stage
of the digital processing of a receive SONET STS-3
or STS-12 bit-serial stream. It converts the bit-serial
155.52 or 622.08 Mbps data stream into a 19.44 or
77.76 Mbyte/sec 8-bit parallel data format.
A loopback mode is provided for diagnostic loopback
(transmitter to receiver).
Frame and Byte Boundary Detection
The frame and byte boundary detection circuitry
searches the incoming data for three consecutive A1
bytes followed immediately by three consecutive A2
bytes. Framing pattern detection is enabled and dis-
abled by the Out-Of-Frame (OOF) input. Detection is
enabled by a rising edge on OOF, and remains en-
abled for the duration that OOF is active. It is
disabled when a framing pattern is detected and
OOF is inactive. When framing pattern detection is
enabled, the framing pattern is used to locate byte
and frame boundaries in the incoming data stream
(RSD or looped transmitter data). The timing genera-
tor block takes the located byte boundary and uses it
to block the incoming data stream into bytes for out-
put on the parallel output data bus (POUT[7:0]). The
frame boundary is reported on the Frame Pulse (FP)
output when any 48-bit pattern matching the framing
pattern is detected on the incoming data stream.
When framing pattern detection is disabled, the byte
boundary is frozen to the location found when detec-
tion was previously enabled. Only framing patterns
aligned to the fixed byte boundary are indicated on
the FP output.
The probability that random data in an STS-3 or STS-
12 stream will generate the 48-bit framing pattern is
extremely small. It is highly improbable that a mimic
pattern would occur within one frame of data. There-
fore, the time to match the first frame pattern and to
verify it with down-stream circuitry, at the next occurrence
of the pattern, is expected to be less than the required
250
μ
s, even for extremely high bit error rates.
Once down-stream overhead circuitry has verified
that the frame and byte synchronization are correct,
the OOF input can be set low to disable the frame
search process from trying to synchronize to a mimic
frame pattern
Serial-to-Parallel Converter
The serial-to-parallel converter consists of three 8-bit
registers. The first is a serial-in, parallel-out shift reg-
ister, which performs serial-to-parallel conversion
clocked by the clock recovery block. The second is
an 8-bit internal holding register, which transfers
data from the serial to parallel register on byte
boundaries as determined by the frame and byte
boundary detection block. On the falling edge of the
free running POCLK, the data in the holding register
is transferred to an output holding register which
drives POUT[7:0].
The delay through the serial-to-parallel converter
can vary from 1.5 to 2.5 byte periods (12 to 20 serial
bit periods) measured from the first bit of an incom-
ing byte to the beginning of the parallel output of that
byte. The variation in the delay is dependent on the
alignment of the internal parallel load timing, which is
synchronized to the data byte boundaries, with respect
to the falling edge of POCLK, which is independent of
the byte boundaries. The advantage of this serial to
parallel converter is that POCLK is neither truncated
nor extended during reframe sequences.
(See Figure 11.)
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