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參數(shù)資料
| 型號： | S3032 |
| 廠商： | APPLIEDMICRO INC |
| 元件分類： | 數(shù)字傳輸電路 |
| 英文描述： | SONET/SDH/ATM OC-3/12 Transceiver W/CDR(頻率可選的SONET/SDH收發(fā)器（完全集成OC-3/12接口器件）) |
| 中文描述： | TRANSCEIVER, PQFP64 |
| 封裝： | 10 MM, PLASTIC, QFP-64 |
| 文件頁數(shù)： | 21/22頁 |
| 文件大?。?/td> | 151K |
| 代理商： | S3032 |
21
S3032
SONET/SDH/ATM OC-3/12 TRANSCEIVER W/CDR
August 18, 2000 / Revision F
S3032 WITH DATA CLOCK SYNCHRONOUS TO
REFERENCE CLOCK
In some applications it is necessary to "forward
clock" the data in a SONET/SDH system. In this ap-
plication the reference clock from which the High
speed serial clock is synthesized and the parallel
data clock both originate from the same (usually
TTL/CMOS) clock source. This application note ex-
plains how the AMCC S3032 can be configured to
operate in this mode.
Clock Control Logic Description
The timing control logic in the S3032 automatically
generates an internal load signal which has a fixed
relationship to the reference clock. The logic takes in
to account the variation of the reference clock to the
internal load signal over temperature and voltage.
The connections required to implement the design
are shown in Figure 14. The setup and hold times for
the PICLK to the data must be met by the controller
ASIC. It is recommended that the data on the falling
edge of the output reference clock be latched in or-
der to meet the required specifications.
Possible Problems
In order to meet the jitter generation specifications
required by SONET, the jitter of the reference clock
must be minimized. It may be difficult to meet the
SONET jitter generation specifications using a refer-
ence clock input with a TTL reference source.
APPLICATION NOTE
ASIC
Data
P/N[7:0]
PICLK
REFCLK
Serial Data
S3032
8
Output
Reference
Clock
Output
Data
Figure 14. S3032 with Data Clocked by Reference Clock
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