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參數(shù)資料
| 型號： | S29GL128N11FFIVH2 |
| 廠商： | SPANSION LLC |
| 元件分類： | PROM |
| 英文描述： | 16M X 16 FLASH 3V PROM, 110 ns, PBGA64 |
| 封裝： | 10 X 13 MM, 1 MM PITCH, LEAD FREE, FBGA-64 |
| 文件頁數(shù)： | 67/74頁 |
| 文件大?。?/td> | 1593K |
| 代理商： | S29GL128N11FFIVH2 |
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May 1, 2006 S29GL-N_01_A0
S29GL-N
5
Data
She e t
1.
General Description
The S29GL256/128N family of devices are 3.0V single power flash memory manufactured using 110 nm
MirrorBit technology. The S29GL256N is a 256 Mbit device, organized as 16,777,216 words or 33,554,432
bytes (x8/x16 option only). The S29GL128N is a 128 Mbit device, organized as 8,388,608 words or
16,777,216 bytes (x8/x16 option only). The devices have a 16-bit wide data bus that can also function as an
8-bit wide data bus by using the BYTE# input. The device can be programmed either in the host system or in
standard EPROM programmers.
Access times as fast as 110 ns are available. Note that each access time has a specific operating voltage
range (VCC) and an I/O voltage range (VIO), as specified in the Product Selector Guide on page 6 and the
Ordering Information on page 10. The devices are offered in a 64-ball Fortified BGA package. Each device
has separate chip enable (CE#), write enable (WE#) and output enable (OE#) controls.
Each device requires only a single 3.0 volt power supply for both read and write functions. In addition to a
VCC input, a high-voltage accelerated program (WP#/ACC) input provides shorter programming times
through increased current. This feature is intended to facilitate factory throughput during system production,
but may also be used in the field if desired.
The devices are entirely command set compatible with the JEDEC single-power-supply Flash standard.
Commands are written to the device using standard microprocessor write timing. Write cycles also internally
latch addresses and data needed for the programming and erase operations.
The sector erase architecture allows memory sectors to be erased and reprogrammed without affecting the
data contents of other sectors. The device is fully erased when shipped from the factory.
Device programming and erasure are initiated through command sequences. Once a program or erase
operation has begun, the host system need only poll the DQ7 (Data# Polling) or DQ6 (toggle) status bits or
monitor the Ready/Busy# (RY/BY#) output to determine whether the operation is complete. To facilitate
programming, an Unlock Bypass mode reduces command sequence overhead by requiring only two write
cycles to program data instead of four.
The Enhanced VersatileI/O (VIO) control allows the host system to set the voltage levels that the device
generates and tolerates on all input levels (address, chip control, and DQ input levels) to the same voltage
level that is asserted on the VIO pin. This allows the device to operate in a 1.8 V or 3 V system environment as
required.
Hardware data protection measures include a low VCC detector that automatically inhibits write operations
during power transitions. Persistent Sector Protection provides in-system, command-enabled protection of
any combination of sectors using a single power supply at VCC. Password Sector Protection prevents
unauthorized write and erase operations in any combination of sectors through a user-defined 64-bit
password.
The Erase Suspend/Erase Resume feature allows the host system to pause an erase operation in a given
sector to read or program any other sector and then complete the erase operation. The Program Suspend/
Program Resume feature enables the host system to pause a program operation in a given sector to read
any other sector and then complete the program operation.
The hardware RESET# pin terminates any operation in progress and resets the device, after which it is then
ready for a new operation. The RESET# pin may be tied to the system reset circuitry. A system reset would
thus also reset the device, enabling the host system to read boot-up firmware from the Flash memory device.
The device reduces power consumption in the standby mode when it detects specific voltage levels on CE#
and RESET#, or when addresses have been stable for a specified period of time.
The Secured Silicon Sector provides a 128-word/256-byte area for code or data that can be permanently
protected. Once this sector is protected, no further changes within the sector can occur.
The Write Protect (WP#/ACC) feature protects the first or last sector by asserting a logic low on the WP# pin.
MirrorBit flash technology combines years of Flash memory manufacturing experience to produce the highest
levels of quality, reliability and cost effectiveness. The device electrically erases all bits within a sector
simultaneously via hot-hole assisted erase. The data is programmed using hot electron injection.
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