參數(shù)資料
型號: S29GL064M90FCIR83
廠商: Spansion Inc.
英文描述: 256,128,64,32,Megabit 3.0 Volt-only Page Mode Flash Memory featuring 0.23 レm MirrorBit Process Technology
中文描述: 256,128,64,32,3.0兆伏安只頁面模式閃存具有0.23レ米MirrorBit工藝技術(shù)
文件頁數(shù): 58/116頁
文件大小: 1656K
代理商: S29GL064M90FCIR83
56
S29GL-M MirrorBit
TM
Flash Family
S29GL-M_00_B6 October 10, 2006
D a t a S h e e t
Factory Locked: Secured Silicon Sector Programmed and Protected At the Factory
In devices with an ESN, the Secured Silicon Sector is protected when the device is shipped from
the factory. The Secured Silicon Sector cannot be modified in any way. An ESN Factory Locked
device has an 16-byte random ESN at addresses 000000h–000007h. Please contact your sales
representative for details on ordering ESN Factory Locked devices.
Customers may opt to have their code programmed by the factory through the Spansion pro-
gramming service (Customer Factory Locked). The devices are then shipped from the factory with
the Secured Silicon Sector permanently locked. Contact your sales representative for details on
using the Spansion programming service.
Write Protect (WP#)
The Write Protect function provides a hardware method of protecting the first or last sector group
without using V
ID
. Write Protect is one of two functions provided by the WP#/ACC input.
If the system asserts V
IL
on the WP#/ACC pin, the device disables program and erase functions
in the first or last sector group independently of whether those sector groups were protected or
unprotected. Note that if WP#/ACC is at V
IL
when the device is in the standby mode, the maxi-
mum input load current is increased (
Table 29
).
Note:
If the system asserts VIH on the WP#/ACC pin, the device reverts to whether the first or last sector was previously
set to be protected or unprotected using the method described in “Sector Group Protection and Unprotection”. Note that
WP# has an internal pullup; when unconnected, WP# is at VIH.
Hardware Data Protection
The command sequence requirement of unlock cycles for programming or erasing provides data
protection against inadvertent writes (
Table 34
and
Table 35
contain command definitions). In ad-
dition, the following hardware data protection measures prevent accidental erasure or
programming, which might otherwise be caused by spurious system level signals during V
CC
power-up and power-down transitions, or from system noise.
Low V
CC
W rite I nhibit
When V
CC
is less than V
LKO
, the device does not accept any write cycles. This protects data during
V
CC
power-up and power-down. The command register and all internal program/erase circuits are
disabled, and the device resets to the read mode. Subsequent writes are ignored until V
CC
is
greater than V
LKO
. The system must provide the proper signals to the control pins to prevent un-
intentional writes when V
CC
is greater than V
LKO
.
W rite Pulse “ Glitch” Protection
Noise pulses of less than 3 ns (typical) on OE#, CE# or WE# do not initiate a write cycle.
Logical I nhibit
Write cycles are inhibited by holding any one of OE# = V
IL
, CE# = V
IH
or WE# = V
IH
. To initiate
a write cycle, CE# and WE# must be a logical zero while OE# is a logical one.
Pow er-Up W rite I nhibit
If WE# = CE# = V
IL
and OE# = V
IH
during power up, the device does not accept commands on
the rising edge of WE#. The internal state machine is automatically reset to the read mode on
power-up.
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