參數(shù)資料
型號(hào): S2070
廠商: Applied Micro Circuits Corp.
英文描述: Fibre Channel and GigaBit Ethernet Transceiver(帶片上鎖相環(huán)的光纖通道/千兆位以太網(wǎng)收發(fā)器)
中文描述: 光纖通道和千兆以太網(wǎng)收發(fā)器(帶片上鎖相環(huán)的光纖通道/千兆位以太網(wǎng)收發(fā)器)
文件頁數(shù): 3/20頁
文件大?。?/td> 498K
代理商: S2070
3
S2070
FIBRE CHANNEL/GIGABIT ETHERNET TRANSCEIVER
March 7, 2001 / Revision G
TRANSMITTER DESCRIPTION
The S2070 transmitter accepts 10-bit parallel input
data and serializes it for transmission over fiber optic
or coaxial cable media. The chip is fully compatible
with the IEEE 802.3z Gigabit Ethernet and ANSI
X3T11 Fibre Channel standards. The S2070 uses a
PLL to generate the serial rate transmit clock. The
transmitter runs at 10 times the TBC input clock, and
operates in either full rate or half rate mode.
Parallel-to-Serial Conversion
The parallel-to-serial converter takes in 10-bit wide
data from the input latch and converts it to a serial
data stream. Parallel data is latched into the trans-
mitter on the positive going edge of TBC. The data is
then clocked into the serial output shift register. The
shift register is clocked by the internally generated
bit clock which is 10x the TBC input frequency. TX[0]
is transmitted first.
Transmit Byte Clock (TBC)
The Transmit Byte Clock (TBC) input must be sup-
plied from a clock source with 100 ppm tolerance to
assure that the transmitted data meets the Fibre
Channel frequency limits. The internal serial clock is
frequency locked to TBC.
TBC is input at full or half rate determined by the
state of the RATEN input. Operating rates are shown
in Table 2.
Transmit Latency
The average transmit latency is 4 parallel clocks.
N
E
T
A
R
t
u
p
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p
n
r
(
e
R
a
P
b
M
y
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e
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q
)
H
e
r
F
(
C
B
T
M
t
u
p
)
p
t
u
b
O
G
(
l
e
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R
S
0
5
2
1
5
2
1
5
2
0
5
2
0
1
5
2
0
1
5
2
6
0
1
5
6
5
6
5
2
6
1
5
2
1
5
5
2
1
5
5
2
1
3
5
Table 2. Operating Rates
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