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參數(shù)資料
| 型號： | S2070 |
| 廠商： | Applied Micro Circuits Corp. |
| 英文描述： | Fibre Channel and GigaBit Ethernet Transceiver(帶片上鎖相環(huán)的光纖通道/千兆位以太網(wǎng)收發(fā)器) |
| 中文描述： | 光纖通道和千兆以太網(wǎng)收發(fā)器（帶片上鎖相環(huán)的光纖通道/千兆位以太網(wǎng)收發(fā)器） |
| 文件頁數(shù)： | 2/20頁 |
| 文件大?。?/td> | 498K |
| 代理商： | S2070 |
2
S2070
FIBRE CHANNEL/GIGABIT ETHERNET TRANSCEIVER
March 7, 2001 / Revision G
S2070 OVERVIEW
The S2070 transmitter and receiver provide serial-
ization and deserialization functions for block en-
coded data to implement a Gigabit Ethernet or Fibre
Channel interface. The S2070 functional block dia-
gram is depicted in Figure 2. The sequence of op-
erations is as follows:
Transmitter
1.10-bit parallel input
2. Parallel-to-serial conversion
3. Serial output
Receiver
1. Clock and data recoverery from serial input
2. Serial-to-parallel conversion
3. Frame detection
4. 10-bit parallel output
The 10-bit parallel data input to the S2070 should be
from a DC-balanced encoding scheme, such as the
8B/10B transmission code, in which information to be
transmitted is encoded 8 bits at a time into 10-bit trans-
mission characters
1
. For reference, Table 1 shows the
mapping of the parallel data to the 8B/10B codes.
Loop Back
Local loopback provides a capability for performing
off-line testing. This is useful for ensuring the
integrity of the serial channel before enabling the
transmission medium. It also allows for system
diagnostics.
FIFO
(4 x 10)
Shift
Register
10
10
PLL Clock
Recovery w/
lock detect
Shift
Register
D
Control
Logic
Comma
Detect
Logic
D
Q
10
TX[0:9]
TBC
RXP
RXN
EWRAP
–LCK_REF
EN_CDET
RBC0
RBC1
COM_DET
RX[0:9]
TXN
TXP
S2070
RATEN
2:1
PLL Clock
Multiplier w/
lock detect
F0 = F1 x 10
Figure 2. Functional Block Diagram
e
B
a
D
]
X
B
o
e
s
e
e
R
R
0
r
1
B
]
X
T
0
1
2
3
4
5
6
7
8
9
8
n
c
b
a
h
p
a
b
c
d
e
i
f
g
h
j
Table 1. Data Mapping to 8B/10B
Alphabetic Representation
1
A.X. Widmer and P.A. Franaszek, "A Byte Oriented DC
Balanced (0,4) 8B/10B Transmission Code," IBM Research
Report RC 9391, May 1982.
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