- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄374647 > S2064 (Applied Micro Circuits Corp.) Quad Serial Backplane Device(用于以太網(wǎng)，光纖通道高速串行數(shù)據(jù)傳送的四收發(fā)器) PDF資料下載
參數(shù)資料
| 型號： | S2064 |
| 廠商： | Applied Micro Circuits Corp. |
| 英文描述： | Quad Serial Backplane Device(用于以太網(wǎng)，光纖通道高速串行數(shù)據(jù)傳送的四收發(fā)器) |
| 中文描述： | 四串行背板設(shè)備（用于以太網(wǎng)，光纖通道高速串行數(shù)據(jù)傳送的四收發(fā)器） |
| 文件頁數(shù)： | 8/33頁 |
| 文件大小： | 340K |
| 代理商： | S2064 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁當前第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁
8
QUAD SERIAL BACKPLANE DEVICE
S2064
October 13, 2000 / Revision G
In addition to data and K characters, the S2064 can
also generate a unique sync sequence consisting of
16 consecutive K28.5 characters. This event is initi-
ated by the simultaneous assertion of KGENx and
SOFx for one clock period. The SOFx and KGENx
inputs should be held low until the sync sequence
has completed. The sync sequence may start with
either a positive or negative parity K28.5. (Depend-
ing on the current running disparity.) The parity of
the second and third K28.5 are inverse with respect
to a valid 8B/10B sequence. Parity of the remaining
K28.5 alternate in accordance with the 8B/10B cod-
ing standard. Thus the parity of the K28.5 pattern
consists of + + - - + - + - + - + - + - + - or - - + + - + -
+ - + - + - + - +. Tables 1a and 1b show the transmit-
ter control signals for both Normal and Channel Lock
mode.
Frequency Synthesizer (PLL)
The S2064 synthesizes a serial transmit clock from
the reference signal. Upon startup, the S2064 will
obtain phase and frequency lock within 2500 bit
times after the start of receiving reference clock in-
puts. Reliable locking of the transmit PLL is assured,
but a lock-detect output is NOT provided.
x
F
O
S
x
N
E
G
K
t
u
p
t
u
O
N
I
D
4
6
0
2
S
0
0
a
D
l
P
d
e
d
o
c
n
E
0
1
d
n
a
2
e
a
T
y
b
d
e
n
d
s
a
r
a
h
]
N
C
I
K
D
1
0
r
a
h
C
5
2
K
1
1
,
+
-
-
+
a
h
-
+
+
-
c
d
w
+
-
+
+
-
6
-
+
1
l
e
-
+
+
-
p
S
+
-
r
-
+
-
-
+
-
-
+
+
-
+
A
F
O
S
B
F
O
S
x
N
E
G
K
t
u
p
t
u
O
4
6
0
2
S
0
0
0
.
D
l
P
d
e
d
o
c
n
E
0
0
1
.
l
n
n
a
h
c
n
o
2
e
a
T
y
b
d
e
n
d
s
a
r
a
h
C
K
1
0
0
.
n
n
a
h
c
r
o
n
o
r
a
h
C
5
2
K
1
0
1
.
l
n
n
a
h
c
n
o
r
a
h
C
c
n
y
S
d
W
6
1
l
e
p
S
X
1
X
r
o
n
o
r
a
h
C
c
n
y
S
d
W
6
1
l
e
n
n
a
p
h
S
c
.
Table 1a. Transmitter Control Signals (Normal Mode, CH_LOCK = 0)
Table 1b. Transmitter Control Signals (Channel Lock Mode, CH_LOCK = 1)
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| S2065 | Quad Serial Backplane Device with Dual I/O(帶雙傳送接收串行I/O的四收發(fā)器) |
| S2066 | Quad GigaBit Ethernet Transceiver(四千兆位以太網(wǎng)收發(fā)器) |
| S2067 | Dual Serial Backplane Transceiver with Dual I/O(帶雙傳送接收串行I/O的雙收發(fā)器) |
| S2068 | Dual GigaBit Ethernet Transceiver(雙千兆位以太網(wǎng)收發(fā)器) |
| S2070 | Fibre Channel and GigaBit Ethernet Transceiver(帶片上鎖相環(huán)的光纖通道/千兆位以太網(wǎng)收發(fā)器) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| S2065A | 制造商:AppliedMicro 功能描述:Backplane Transceiver 208-Pin TBGA |
| S2065J | 功能描述:SCR 65A 200V RoHS:否 制造商:STMicroelectronics 最大轉(zhuǎn)折電流 IBO:480 A 額定重復(fù)關(guān)閉狀態(tài)電壓 VDRM:600 V 關(guān)閉狀態(tài)漏泄電流（在 VDRM IDRM 下）:5 uA 開啟狀態(tài) RMS 電流 (It RMS): 正向電壓下降:1.6 V 柵觸發(fā)電壓 (Vgt):1.3 V 最大柵極峰值反向電壓:5 V 柵觸發(fā)電流 (Igt):35 mA 保持電流（Ih 最大值）:75 mA 安裝風格:Through Hole 封裝 / 箱體:TO-220 封裝:Tube |
| S2065J | 制造商:Littelfuse 功能描述:Thyristor Thyristor/Triac Type:SCR |
| S2065J_ | 功能描述:SCR - Use 576-S2065J RoHS:否 制造商:STMicroelectronics 最大轉(zhuǎn)折電流 IBO:480 A 額定重復(fù)關(guān)閉狀態(tài)電壓 VDRM:600 V 關(guān)閉狀態(tài)漏泄電流（在 VDRM IDRM 下）:5 uA 開啟狀態(tài) RMS 電流 (It RMS): 正向電壓下降:1.6 V 柵觸發(fā)電壓 (Vgt):1.3 V 最大柵極峰值反向電壓:5 V 柵觸發(fā)電流 (Igt):35 mA 保持電流（Ih 最大值）:75 mA 安裝風格:Through Hole 封裝 / 箱體:TO-220 封裝:Tube |
| S2065JTP | 功能描述:SCR SCR 200V 65A Iso RoHS:否 制造商:STMicroelectronics 最大轉(zhuǎn)折電流 IBO:480 A 額定重復(fù)關(guān)閉狀態(tài)電壓 VDRM:600 V 關(guān)閉狀態(tài)漏泄電流（在 VDRM IDRM 下）:5 uA 開啟狀態(tài) RMS 電流 (It RMS): 正向電壓下降:1.6 V 柵觸發(fā)電壓 (Vgt):1.3 V 最大柵極峰值反向電壓:5 V 柵觸發(fā)電流 (Igt):35 mA 保持電流（Ih 最大值）:75 mA 安裝風格:Through Hole 封裝 / 箱體:TO-220 封裝:Tube |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。