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參數(shù)資料
| 型號： | S2064 |
| 廠商： | Applied Micro Circuits Corp. |
| 英文描述： | Quad Serial Backplane Device(用于以太網(wǎng)，光纖通道高速串行數(shù)據(jù)傳送的四收發(fā)器) |
| 中文描述： | 四串行背板設(shè)備（用于以太網(wǎng)，光纖通道高速串行數(shù)據(jù)傳送的四收發(fā)器） |
| 文件頁數(shù)： | 14/33頁 |
| 文件大?。?/td> | 340K |
| 代理商： | S2064 |
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14
QUAD SERIAL BACKPLANE DEVICE
S2064
October 13, 2000 / Revision G
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Table 7. Output Clock Mode
CHANNEL LOCKING/RE-LOCKING
PROCEDURE
The Channel locking/relocking procedures are sum-
marized below. Following these procedures will in-
sure proper CHANNEL LOCK operation of the
device. When powered up, the S2064 will lock to the
received data within approximately 2500 bit times.
The CRU must report lock for approximately 32,000
REFCLK periods (320
μ
s) before channel locking is
enabled.
1. Insure that the S2064 is in the “No Sync” state.
This can be accomplished by resetting the device
by toggling SOFD low, or by de-asserting the
channel lock for several clock periods and then
re-asserting.
2. Transmit the appropriate synchronization se-
quence. Four K28.5 characters or the 16 word
SYNC sequence can be used to de-skew the
DOUT FIFOs. The 16 word SYNC character can
be generated by asserting SOFx=1 and
KGENx=1.
3. Wait for “channel lock detected” as defined by
Table 6.
The S2064 will enter the “No Sync” state if: any CRU
loses lock, if the CH_LOCK signal is de-asserted, if
four or more consecutive decoder errors are ob-
served, or if the decoder error rate exceeds 50% in a
block of 16 bytes, or if SOFD is low. If desired, the
CRU lock status of each channel can be checked by
de-asserting CH_LOCK and confirming that “Loss of
Sync” status (Table 6) is not reported by any chan-
nel. To reacquire Sync after moving to the “No Sync”
state, repeat steps 2 and 3 above.
8B/10B Decoding
After serial to parallel conversion, the S2064 pro-
vides 8B/10B decoding of the data. The received 10-
bit codeword is decoded to recover the original 8-bit
data. The decoder also checks for errors and flags,
either invalid codeword errors or running disparity
errors by assertion of the ERRx signal. Error type is
determined by examining the EOF output in accor-
dance with Table 6. When more than one reportable
condition occurs simultaneously, reporting is in ac-
cordance with the rank assigned by Table 6.
Data Output
Data is output on the DOUT[0:7] outputs. K-characters
are flagged using the KFLAG signal. The EOF (with
KFLAG) is used to indicate the reception of a valid
K28.5 character. Invalid codewords and decoding er-
rors are indicated on the ERR output. KFLAG, EOF,
and ERR are buffered with the data in the FIFO to
insure that all outputs are synchronized at the S2064
outputs. Errors are reported independently for each
channel in both CHANNEL LOCK mode and NOR-
MAL mode operation.
The S2064 TTL outputs are optimized to drive 65
line impedance. Internal source matching provides
good performance on unterminated lines of reason-
able length.
Parallel Output Clock Rate
Two output clock modes are supported, as shown in
Table 7. When CMODE is HIGH, a complementary
TTL clock at the data rate is provided on the RCxP/N
outputs. Data should be clocked on the rising edge
of RCxP. When CMODE is LOW, a complementary
TTL clock at 1/2 the data rate is provided. Data
should be latched on the rising edge of RCxP and
the rising edge of RCxN.
In Fibre Channel and Gigabit Ethernet applications,
multiple consecutive K28.5 characters cannot be
generated. However, for serial backplane applica-
tions this can occur. The S2064 must be able to
operate properly when multiple K28.5 characters are
received. After the first K28.5 is detected and
aligned, the RCxP/N clock will operate without
glitches or loss of cycles.
相關(guān)PDF資料 |
PDF描述 |
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| S2065 | Quad Serial Backplane Device with Dual I/O(帶雙傳送接收串行I/O的四收發(fā)器) |
| S2066 | Quad GigaBit Ethernet Transceiver(四千兆位以太網(wǎng)收發(fā)器) |
| S2067 | Dual Serial Backplane Transceiver with Dual I/O(帶雙傳送接收串行I/O的雙收發(fā)器) |
| S2068 | Dual GigaBit Ethernet Transceiver(雙千兆位以太網(wǎng)收發(fā)器) |
| S2070 | Fibre Channel and GigaBit Ethernet Transceiver(帶片上鎖相環(huán)的光纖通道/千兆位以太網(wǎng)收發(fā)器) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| S2065A | 制造商:AppliedMicro 功能描述:Backplane Transceiver 208-Pin TBGA |
| S2065J | 功能描述:SCR 65A 200V RoHS:否 制造商:STMicroelectronics 最大轉(zhuǎn)折電流 IBO:480 A 額定重復(fù)關(guān)閉狀態(tài)電壓 VDRM:600 V 關(guān)閉狀態(tài)漏泄電流（在 VDRM IDRM 下）:5 uA 開啟狀態(tài) RMS 電流 (It RMS): 正向電壓下降:1.6 V 柵觸發(fā)電壓 (Vgt):1.3 V 最大柵極峰值反向電壓:5 V 柵觸發(fā)電流 (Igt):35 mA 保持電流（Ih 最大值）:75 mA 安裝風(fēng)格:Through Hole 封裝 / 箱體:TO-220 封裝:Tube |
| S2065J | 制造商:Littelfuse 功能描述:Thyristor Thyristor/Triac Type:SCR |
| S2065J_ | 功能描述:SCR - Use 576-S2065J RoHS:否 制造商:STMicroelectronics 最大轉(zhuǎn)折電流 IBO:480 A 額定重復(fù)關(guān)閉狀態(tài)電壓 VDRM:600 V 關(guān)閉狀態(tài)漏泄電流（在 VDRM IDRM 下）:5 uA 開啟狀態(tài) RMS 電流 (It RMS): 正向電壓下降:1.6 V 柵觸發(fā)電壓 (Vgt):1.3 V 最大柵極峰值反向電壓:5 V 柵觸發(fā)電流 (Igt):35 mA 保持電流（Ih 最大值）:75 mA 安裝風(fēng)格:Through Hole 封裝 / 箱體:TO-220 封裝:Tube |
| S2065JTP | 功能描述:SCR SCR 200V 65A Iso RoHS:否 制造商:STMicroelectronics 最大轉(zhuǎn)折電流 IBO:480 A 額定重復(fù)關(guān)閉狀態(tài)電壓 VDRM:600 V 關(guān)閉狀態(tài)漏泄電流（在 VDRM IDRM 下）:5 uA 開啟狀態(tài) RMS 電流 (It RMS): 正向電壓下降:1.6 V 柵觸發(fā)電壓 (Vgt):1.3 V 最大柵極峰值反向電壓:5 V 柵觸發(fā)電流 (Igt):35 mA 保持電流（Ih 最大值）:75 mA 安裝風(fēng)格:Through Hole 封裝 / 箱體:TO-220 封裝:Tube |
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