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參數(shù)資料
| 型號： | S2062 |
| 廠商： | Applied Micro Circuits Corp. |
| 英文描述： | Dual Serial Backplane Transceiver(用于以太網(wǎng)，光纖通道高速串行數(shù)據(jù)傳送的雙收發(fā)器) |
| 中文描述： | 雙串行背板收發(fā)器（用于以太網(wǎng)，光纖通道高速串行數(shù)據(jù)傳送的雙收發(fā)器） |
| 文件頁數(shù)： | 8/27頁 |
| 文件大?。?/td> | 289K |
| 代理商： | S2062 |
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8
DUAL SERIAL BACKPLANE DEVICE
S2062
October 13, 2000 / Revision C
Table 3. K Character Generation (SOFx = 0)
K
a
r
r
e
a
h
C
]
N
I
D
N
E
G
K
+
D
R
t
n
e
r
u
C
-
D
R
t
n
e
r
u
C
s
n
e
m
m
o
C
j
g
f
i
d
c
b
a
j
g
f
i
d
c
b
a
0
2
1
2
2
2
3
2
4
2
5
2
6
2
7
2
7
2
7
2
7
2
7
3
K
K
K
K
K
K
K
K
K
K
K
K
0
0
0
0
0
0
0
0
1
1
1
0
0
0
0
0
0
0
0
0
1
1
0
1
1
1
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
0
1
0
1
0
1
1
1
1
1
0
0
1
1
0
0
1
1
1
1
1
1
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
1
0
1
0
1
1
1
0
1
1
1
1
1
1
0
1
1
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
1
1
1
1
1
1
1
1
0
0
1
0
1
1
1
1
1
1
1
1
0
0
0
1
0
1
1
1
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
0
1
0
1
0
0
0
1
0
0
0
0
0
0
1
0
0
0
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
1
1
1
1
1
0
1
1
0
0
0
0
0
0
0
0
1
1
0
1
0
0
0
0
0
0
0
0
1
1
1
0
r
a
h
C
c
n
y
S
Table 4. Data to 8B/10B Alphabetic Representation
e
B
a
D
]
U
O
D
r
]
N
I
D
0
1
2
3
4
5
6
7
8
9
n
o
e
s
e
e
R
c
m
u
n
a
h
p
B
0
1
B
8
a
b
c
d
e
i
f
g
h
j
Table 5. Operating Rates
E
T
A
R
L
E
S
K
L
C
K
c
L
n
C
e
u
F
E
q
e
R
r
y
F
t
u
p
t
u
O
l
e
S
e
R
O
n
K
e
L
u
C
q
T
e
r
y
c
F
0
0
0
1
R
D
S
z
H
G
3
–
7
7
0
1
R
D
S
0
1
0
2
R
D
S
z
H
G
3
–
7
7
0
1
R
D
S
1
0
0
1
R
D
S
z
H
G
5
6
3
0
1
R
D
S
1
1
0
2
R
D
S
z
H
G
5
6
3
0
1
R
D
S
Reference Clock Input
The reference clock input must be supplied with a
low-jitter clock source. All reference clocks in a sys-
tem must be within 200 ppm of each other to insure
that the clock recovery units can lock to the serial
data.
The frequency of the reference clock must be either
1/10 the serial data rate, CLKSEL = 0, or 1/20 the
serial data rate, CLKSEL=1. In both cases the fre-
quency of the parallel word rate output, TCLKO, is
constant at 1/10 the serial data rate. See Table 5.
Serial Data Outputs
The S2062 provides LVPECL level serial outputs. Each
high speed output should be provided with a resistor to
VSS (Gnd) near the device. A value of 4.5 K
provides
optimal performance with minimum impact on power
dissipation. The resistance may be as low as 450
,
but this will dissipate additional power with no sub-
stantive performance improvement. Outputs are de-
signed to perform optimally when AC-coupled.
Transmit FIFO Initialization
The transmit FIFO must be initialized after stable
delivery of data and TCLK to the parallel interface,
and before entering the normal operational state of
the circuit. FIFO initialization is performed upon the
de-assertion of the RESET signal. TCLKO will oper-
ate normally regardless of the state of RESET.
Note: SDR = Serial Data Rate.
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相關(guān)代理商/技術(shù)參數(shù) |
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| S2065J | 功能描述:SCR 65A 200V RoHS:否 制造商:STMicroelectronics 最大轉(zhuǎn)折電流 IBO:480 A 額定重復(fù)關(guān)閉狀態(tài)電壓 VDRM:600 V 關(guān)閉狀態(tài)漏泄電流（在 VDRM IDRM 下）:5 uA 開啟狀態(tài) RMS 電流 (It RMS): 正向電壓下降:1.6 V 柵觸發(fā)電壓 (Vgt):1.3 V 最大柵極峰值反向電壓:5 V 柵觸發(fā)電流 (Igt):35 mA 保持電流（Ih 最大值）:75 mA 安裝風(fēng)格:Through Hole 封裝 / 箱體:TO-220 封裝:Tube |
| S2065J | 制造商:Littelfuse 功能描述:Thyristor Thyristor/Triac Type:SCR |
| S2065J_ | 功能描述:SCR - Use 576-S2065J RoHS:否 制造商:STMicroelectronics 最大轉(zhuǎn)折電流 IBO:480 A 額定重復(fù)關(guān)閉狀態(tài)電壓 VDRM:600 V 關(guān)閉狀態(tài)漏泄電流（在 VDRM IDRM 下）:5 uA 開啟狀態(tài) RMS 電流 (It RMS): 正向電壓下降:1.6 V 柵觸發(fā)電壓 (Vgt):1.3 V 最大柵極峰值反向電壓:5 V 柵觸發(fā)電流 (Igt):35 mA 保持電流（Ih 最大值）:75 mA 安裝風(fēng)格:Through Hole 封裝 / 箱體:TO-220 封裝:Tube |
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