參數(shù)資料
型號(hào)： S2062
廠商： Applied Micro Circuits Corp.
英文描述： Dual Serial Backplane Transceiver(用于以太網(wǎng)，光纖通道高速串行數(shù)據(jù)傳送的雙收發(fā)器)
中文描述： 雙串行背板收發(fā)器（用于以太網(wǎng)，光纖通道高速串行數(shù)據(jù)傳送的雙收發(fā)器）
文件頁(yè)數(shù)： 7/27頁(yè)
文件大?。?/td> 289K
代理商： S2062
7
S2062
DUAL SERIAL BACKPLANE DEVICE
October 13, 2000 / Revision C
Figure 6. DIN Data Clocking with TCLK
A special input, SOF, is provided for each channel to
simplify the generation of the K28.5 character. When
SOF is asserted, the K28.5 character is generated
regardless of the data on the parallel input. The K28.5
character can be of either positive or negative parity,
depending on the current running disparity. Table 4
shows the mapping of the 8B/10B characters repre-
sentation. Data is transmitted bit “a” or DIN[0] first.
In addition to data and K characters, the S2062 can
also generate a unique sync sequence consisting of
16 consecutive K28.5 characters. This event is initi-
ated by the simultaneous assertion of KGENx and
SOFx for one clock period. The SOFx and KGENx
inputs should be held low until the sync sequence has
completed. The sync sequence may start with either a
positive or negative parity K28.5. (Depending on the
current running disparity.) The parity of the second
and third K28.5 are inverse with respect to a valid 8B/
REFCLK
S2062
VCO/10 or VCO/20
TCLKx
DINx[0:7]
REF
OSCILLATOR
MAC
ASIC
TCLKO
PLL
1
1. A.X. Widner and P.A. Franaszek, "A Byte-Oriented DC Bal-
anced (0,4) 8B/10B Transmission Code," IBM Research Report
RC9391, May 1982.
x
F
O
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x
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K
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2
6
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a
h
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a
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3
1
0
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a
h
C
5
2
K
1
1
,
+
-
-
+
a
h
-
+
+
-
c
d
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+
-
+
+
-
6
-
+
1
l
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-
+
+
-
p
S
+
-
r
-
+
-
-
+
-
-
+
+
-
+
10B sequence. Parity of the remaining K28.5 alter-
nate in accordance with the 8B/10B coding standard.
Thus, the parity of the K28.5 pattern consists of + + - -
+ - + - + - + - + - + - or - - + + - + - + - + - + - + - +.
Table 2 shows the transmitter control signals.
Frequency Synthesizer (PLL)
The S2062 synthesizes a serial transmit clock from
the reference signal. Upon startup, the S2062 will
obtain phase and frequency lock within 2500 bit
times after the start of receiving reference clock in-
puts. Reliable locking of the transmit PLL is assured,
but a lock-detect output is NOT provided.
Table 2. Transmitter Control Signals
Note that internal synchronization of FIFOs is performed upon
de-assertion of RESET.
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Table 1. Input Modes
Figure 7. DIN Clocking with REFCLK
REFCLK
S2062
TCLKx
DINx[0:7]
REF
OSCILLATOR
MAC
ASIC
TCLKO
PLL
VC0/10
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