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參數(shù)資料
| 型號： | S2062 |
| 廠商： | Applied Micro Circuits Corp. |
| 英文描述： | Dual Serial Backplane Transceiver(用于以太網(wǎng)，光纖通道高速串行數(shù)據(jù)傳送的雙收發(fā)器) |
| 中文描述： | 雙串行背板收發(fā)器（用于以太網(wǎng)，光纖通道高速串行數(shù)據(jù)傳送的雙收發(fā)器） |
| 文件頁數(shù)： | 6/27頁 |
| 文件大?。?/td> | 289K |
| 代理商： | S2062 |
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6
DUAL SERIAL BACKPLANE DEVICE
S2062
October 13, 2000 / Revision C
TRANSMITTER DESCRIPTION
The transmitter section of the S2062 contains a
single PLL which is used to generate the serial rate
transmit clock for all transmitters. Two channels are
provided with a variety of options regarding input
clocking and loopback. The transmitters can operate
in the range of 0.77 GHz to 1.3 GHz, 10 or 20 times
the reference clock frequency.
Data Input
The S2062 has been designed to simplify the paral-
lel interface data transfer and provides the utmost in
flexibility regarding clocking of parallel data. Prior, or
less sophisticated, implementations of this function
have either forced the user to synchronize transmit
data to the reference clock or to provide the output
clock as a reference to the PLL, resulting in in-
creased jitter at the serial interface. The S2062 in-
corporates a unique FIFO structure on both the
parallel inputs and the parallel outputs which en-
ables the user to provide a “clean” reference source
for the PLL and to accept a separate external clock
which is used exclusively to reliably clock data into
the device.
Data is input to each channel of the S2062 nominally
as a 10 bit wide word. This consists of eight data bits
of user data, KGEN, and SOF. An input FIFO and a
clock input, TCLKx, are provided for each channel of
the S2062. The S2062 can be configured to use ei-
ther the TCLKx (TCLK MODE) input or the REFCLK
input (REFCLK MODE). In TCLK or REFCLK mode,
each byte of data is clocked into its FIFO with the
TCLKx provided with each byte. Table 1 provides a
summary of the input modes for the S2062.
Operation in the TCLK MODE makes it easier for
users to meet the relatively narrow setup and hold
time window required by the parallel 10-bit interface.
The TCLK signal is used to clock the data into an
internal holding register and the S2062 synchronizes
its internal data flow to insure stable operation. How-
ever, regardless of the clock mode, REFCLK is al-
ways the VCO reference clock. This facilitates the
provision of a clean reference clock resulting in mini-
mum jitter on the serial output. The TCLK must be
frequency locked to REFCLK, but may have an arbi-
trary but fixed phase relationship. Adjustment of in-
ternal timing of the S2062 is performed during reset.
Once synchronized, the S2062 can tolerate up to
±
3ns of phase drift between TCLK and REFCLK.
Figure 6 demonstrates the flexibility afforded by the
S2062. A low jitter reference is provided directly to
the S2062 at either 1/10 or 1/20 the serial data rate.
This insures minimum jitter in the synthesized clock
used for serial data transmission. A system clock
output at the parallel word rate, TCLKO, is derived
from the PLL and provided to the upstream circuit as
a system clock. The frequency of this output is con-
stant at the parallel word rate, 1/10 the serial data
rate, regardless of whether the reference is provided
at 1/10 or 1/20 the serial data rate. This clock can be
buffered as required without concern about added
delay. There is no phase requirement between
TCLKO and TCLKx, which is provided back to the
S2062, other than that they remain within
±
3ns of
the phase relationship established at reset.
The S2062 also supports the traditional REFCLK
(TBC) clocking found in Fibre Channel and Gigabit
Ethernet applications and is illustrated in Figure 7.
Half Rate Operation
The S2062 supports full and 1/2 rate operation for all
modes of operation. When RATE is LOW, the S2062
serial data rate equals the VCO frequency. When
RATE is HIGH, the VCO is divided by 2 before being
provided to the chip. Thus the S2062 can support
Fibre Channel and serial backplane functions at both
full and 1/2 the VCO rate.
8B/10B Coding
The S2062 provides 8B/10B line coding for each
channel. The 8B/10B transmission code includes se-
rial encoding and decoding rules, special characters,
and error control. Information is encoded, 8 bits at a
time, into a 10 bit transmission character. The char-
acters defined by this code ensure that enough tran-
sitions are present in the serial bit stream to make
clock recovery possible at the receiver. The encod-
ing also greatly increases the likelihood of detecting
any single or multiple errors that might occur during
the transmission and reception of data
1
.
The 8B/10B transmission code includes D-charac-
ters, used for data transmission, and K-characters,
used for control or protocol functions. Each D-char-
acter and K-character has a positive and a negative
parity version. The parity of each codeword is se-
lected by the encoder to control the running disparity
of the data stream. K-character generation is con-
trolled individually for each channel using the
KGENx input. When KGEN is asserted, the data on
the parallel input is mapped into the corresponding
control character. The parity of the K-character is
selected to minimize running disparity in the serial
data stream. Table 3 lists the K characters sup-
ported by the S2062 and identifies the mapping of
the DIN[7:0] bits to each character.
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