參數(shù)資料
型號(hào)： S2062
廠商： Applied Micro Circuits Corp.
英文描述： Dual Serial Backplane Transceiver(用于以太網(wǎng)，光纖通道高速串行數(shù)據(jù)傳送的雙收發(fā)器)
中文描述： 雙串行背板收發(fā)器（用于以太網(wǎng)，光纖通道高速串行數(shù)據(jù)傳送的雙收發(fā)器）
文件頁(yè)數(shù)： 1/27頁(yè)
文件大小： 289K
代理商： S2062
1
S2062
S2062
DUAL SERIAL BACKPLANE DEVICE
October 13, 2000 / Revision C
DEVICE
SPECIFICATION
Figure 1. Typical Dual Gigabit Ethernet Application
FEATURES
Broad operating rate range (0.77 - 1.3 GHz)
- 1062 MHz (Fibre Channel)
- 1250 MHz (Gigabit Ethernet) line rates
- 1/2 Rate Operation
Dual Transmitter with phase-locked loop (PLL)
clock synthesis from low speed reference
Dual Receiver PLL provides clock and data
recovery
Internally series terminated TTL outputs
On-chip 8B/10B line encoding and decoding for
two separate parallel 8-bit channels
2x8 Bit parallel TTL interface
Low-jitter serial PECL interface
Local Loopback
Interfaces with coax, twinax, or fiber optics
Single +3.3V supply, 1.37 W power dissipation
Compact 21mm x 21mm 156 TBGA package
APPLICATIONS
Ethernet Backbones
Workstation
Frame buffer
Switched networks
Data broadcast environments
Proprietary extended backplanes
GENERAL DESCRIPTION
The S2062 facilitates high-speed serial transmission
of data in a variety of applications including Gigabit
Ethernet, Fibre Channel, serial backplanes, and pro-
prietary point to point links. The chip provides two
separate transceivers which can be operated indi-
vidually for a data capacity of >2 Gbps.
Each bi-directional channel provides 8B/10B coding/
decoding, parallel to serial and serial to parallel con-
version, clock generation/recovery, and framing. The
on-chip transmit PLL synthesizes the high-speed
clock from a low-speed reference. The on-chip dual
receive PLL is used for clock recovery and data re-
timing on the two independent data inputs. The
transmitter and receiver each support differential
PECL-compatible I/O for copper or fiber optic com-
ponent interfaces with excellent signal integrity. Lo-
cal loopback mode allows for system diagnostics.
The chip requires a 3.3V power supply and dissi-
pates 1.37 watts.
Figure 1 shows the S2062 and S2068 in a Gigabit
Ethernet application. Figure 2 combines the
S2062 with a crosspoint switch to demonstrate a
serial backplane application. Figure 3 is the input/
output diagram. Figures 4 and 5 show the transmit
and receive block diagrams, respectively.
MAC
(ASIC)
S2062
DUAL
GIGABIT
ETHERNET
INTERFACE
MAC
(ASIC)
TO SERIAL BACKPLANE
S2068
GE INTERFACE
SERIAL BP DRIVER
相關(guān)PDF資料
PDF描述
S2064 Quad Serial Backplane Device(用于以太網(wǎng)，光纖通道高速串行數(shù)據(jù)傳送的四收發(fā)器)
S2065 Quad Serial Backplane Device with Dual I/O(帶雙傳送接收串行I/O的四收發(fā)器)
S2066 Quad GigaBit Ethernet Transceiver(四千兆位以太網(wǎng)收發(fā)器)
S2067 Dual Serial Backplane Transceiver with Dual I/O(帶雙傳送接收串行I/O的雙收發(fā)器)
S2068 Dual GigaBit Ethernet Transceiver(雙千兆位以太網(wǎng)收發(fā)器)
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
S2062TB 制造商:AppliedMicro 功能描述:Backplane Transceiver 156-Pin TBGA
S2065A 制造商:AppliedMicro 功能描述:Backplane Transceiver 208-Pin TBGA
S2065J 功能描述:SCR 65A 200V RoHS:否 制造商:STMicroelectronics 最大轉(zhuǎn)折電流 IBO:480 A 額定重復(fù)關(guān)閉狀態(tài)電壓 VDRM:600 V 關(guān)閉狀態(tài)漏泄電流（在 VDRM IDRM 下）:5 uA 開(kāi)啟狀態(tài) RMS 電流 (It RMS): 正向電壓下降:1.6 V 柵觸發(fā)電壓 (Vgt):1.3 V 最大柵極峰值反向電壓:5 V 柵觸發(fā)電流 (Igt):35 mA 保持電流（Ih 最大值）:75 mA 安裝風(fēng)格:Through Hole 封裝 / 箱體:TO-220 封裝:Tube
S2065J 制造商:Littelfuse 功能描述:Thyristor Thyristor/Triac Type:SCR
S2065J_ 功能描述:SCR - Use 576-S2065J RoHS:否 制造商:STMicroelectronics 最大轉(zhuǎn)折電流 IBO:480 A 額定重復(fù)關(guān)閉狀態(tài)電壓 VDRM:600 V 關(guān)閉狀態(tài)漏泄電流（在 VDRM IDRM 下）:5 uA 開(kāi)啟狀態(tài) RMS 電流 (It RMS): 正向電壓下降:1.6 V 柵觸發(fā)電壓 (Vgt):1.3 V 最大柵極峰值反向電壓:5 V 柵觸發(fā)電流 (Igt):35 mA 保持電流（Ih 最大值）:75 mA 安裝風(fēng)格:Through Hole 封裝 / 箱體:TO-220 封裝:Tube
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫(xiě)一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*