
Page 8
Epson Research and Development
Vancouver Design Center
S1D13A05
Register Summary
X40A-R-001-01
Issue Date: 02/01/21
Endpoint 4 Transmit FIFO Status Register
REG[402Ch]
Default = 01h
Read/Write
n/a
Transmit
FIFO Valid
Transmit
FIFO Flush
Transmit
FIFO
Overflow
Reserved
Transmit
FIFO Full
(read only)
Transmit
FIFO
Empty
(read only)
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Endpoint 4 Maximum Packet Size Register
REG[402Eh]
Default = 08h
Read/Write
n/a
Endpoint 4 Max Packet Size bits 7-0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Revision Register
REG[4030h]
Default = 01h
Read Only
n/a
Chip Revision bits 7-0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
USB Status Register
REG[4032h]
Default = 00h
Read/Write
n/a
Suspend
Control
USB
Endpoint 4
STALL
USB
Endpoint 4
NAK
USB
Endpoint 4
ACK
USB
Endpoint 3
STALL
USB
Endpoint 3
NAK
USB
Endpoint 3
ACK
Endpoint 2
Valid
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Frame Counter MSB Register
REG[4034h]
Default = 00h
Read Only
n/a
Frame Counter bits 10-8
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Frame Counter LSB Register
REG[4036h]
Default = 00h
Read Only
n/a
Frame Counter bits 7-0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Extended Register Index
REG[4038h]
Default = 00h
Read/Write
n/a
Extended Register Index bits 7-0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Extended Register Data
REG[403Ah]
Default = 04h
Read/Write
n/a
Extended Register Data bits 7-0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Vendor ID MSB
REG[403Ah], Index[00h]
Default = 04h
Read/Write
Vendor ID LSB
REG[403Ah], Index[01h]
Default = B8h
Read/Write
Vendor ID bits 15-8
Vendor ID bits 7-0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
Product ID MSB
REG[403Ah], Index[02h]
Default = 88h
Read/Write
Product ID LSB
REG[403Ah], Index[03h]
Default = 21h
Read/Write
Product ID bits 15-8
Product ID bits 7-0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
Release Number MSB
REG[403Ah], Index[04h]
Default = 01h
Read/Write
Release Number LSB
REG[403Ah], Index[05h]
Default = 00h
Read/Write
Release Number bits 15-8
Release Number bits 7-0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
Receive FIFO Almost Full Threshold
REG[403Ah], Index[06h]
Default = 3Ch
Read/Write
Transmit FIFO Almost Empty Threshold
REG[403Ah], Index[07h]
Default = 04h
Read/Write
n/a
Receive FIFO Almost Full Threshold bits 5-0
n/a
Transmit FIFO Almost Empty Threshold bits 5-0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
USB Control
REG[403Ah], Index[08h]
Default = 01h
Read/Write
Maximum Power Consumption
REG[403Ah], Index[09h]
Default = FAh
Read/Write
n/a
USB String
Enable
Maximum Current bits 7-0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
Packet Control
REG[403Ah], Index[0Ah]
Default = 00h
Read/Write
Reserved
REG[403Ah], Index[0Bh]
Default = 00h
Read/Write
EP4 Data
Toggle
EP3 Data
Toggle
EP2 Data
Toggle
EP1 Data
Toggle
Reserved
n/a
Reserved
n/a
Reserved
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
FIFO Control
REG[403Ah], Index[0Ch]
Default = 00h
Read/Write
n/a
Transmit
FIFO Valid
Mode
7
6
5
4
3
2
1
0
USBFC Input Control Register
REG[4040h]
Default = 0Dh
Read/Write
n/a
USCMPEN
Reserved
ISO
WAKEUP
Reserved
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reserved
REG[4042h]
Default = 1Dh
Read Only
n/a
Reserved
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0