
Epson Research and Development
Page 7
Vancouver Design Center
Register Summary
S1D13A05
Issue Date: 02/01/21
X40A-R-001-01
USB REGISTERS
Control Register
REG[4000h]
Default = 00h
Read/Write
n/a
USBClk
Enable
Software
EOT
USB
Enable
Endpoint 4
Stall
Endpoint 3
Stall
USB Setup
Reserved
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Interrupt Enable Register 0
REG[4002h]
Default = 00h
Read/Write
n/a
Suspend
Request
Interrupt
Enable
SOF
Interrupt
Enable
Reserved
Endpoint 4
Interrupt
Enable
Endpoint 3
Interrupt
Enable
Endpoint 2
Interrupt
Enable
Endpoint 1
Interrupt
Enable
n/a
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Interrupt Status Register 0
REG[4004h]
Default = 00h
Read/Write
n/a
Suspend
Request
Interrupt
Status
SOF
Interrupt
Status
Reserved
Endpoint 4
Interrupt
Status
Endpoint 3
Interrupt
Status
Endpoint 2
Interrupt
Status
Endpoint 1
Interrupt
Status
Upper
Interrupt
Active
(read only)
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Interrupt Enable Register 1
REG[4006h]
Default = 00h
Read/Write
n/a
Transmit
FIFO
Almost
Empty
Interrupt
Enable
Receive
FIFO
Almost Full
Interrupt
Enable
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Interrupt Status Register 1
REG[4008h]
Default = 00h
Read/Write
n/a
Transmit
FIFO
Almost
Empty
Status
Receive
FIFO
Almost Full
Status
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Endpoint 1 Index Register
REG[4010h]
Default = 00h
Read Only
n/a
Endpoint 1 Index bits 2-0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Endpoint 1 Receive Mailbox Data Register
REG[4012h]
Default = 00h
Read Only
n/a
Endpoint 1 Receive Mailbox Data bits 7-0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Endpoint 2 Index Register
REG[4018h]
Default = 00h
Read/Write
n/a
Endpoint 2 Index bits 2-0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Endpoint 2 Transmit Mailbox Data Register
REG[401Ah]
Default = 00h
Read/Write
n/a
Endpoint 2 Transmit Mailbox Data bits 7-0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Endpoint 2 Interrupt Polling Interval Register
REG[401Ch]
Default = FFh
Read/Write
n/a
Endpoint 2 Interrupt Polling Interval bits 7-0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Endpoint 3 Receive FIFO Data Register
REG[4020h]
Default = 00h
Read Only
n/a
Endpoint 3 Receive FIFO Data bits 7-0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Endpoint 3 Receive FIFO Count Register
REG[4022h]
Default = 00h
Read Only
n/a
Endpoint 3 Receive FIFO Count bits 7-0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Endpoint 3 Receive FIFO Status Register
REG[4024h]
Default = 01h
Read/Write
n/a
Receive
FIFO Flush
Receive
FIFO
Overflow
Receive
FIFO
Underflow
Receive
FIFO Full
(read only)
Receive
FIFO
Empty
(read only)
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Endpoint 3 Maximum Packet Size Register
REG[4026h]
Default = 08h
Read/Write
n/a
Endpoint 3 Max Packet Size bits 7-0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Endpoint 4 Transmit FIFO Data Register
REG[4028h]
Default = 00h
Write Only
n/a
Endpoint 4 Transmit FIFO Data bits 7-0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Endpoint 4 Transmit FIFO Count Register
REG[402Ah]
Default = 00h
Read Only
n/a
Endpoint 4 Transmit FIFO Count bits 7-0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0