- 您現(xiàn)在的位置：買(mǎi)賣(mài)IC網(wǎng) > PDF目錄98068 > S1C88104P0A0100 8-BIT, MROM, 8.2 MHz, MICROCONTROLLER, PBGA240 PDF資料下載
參數(shù)資料
| 型號(hào)： | S1C88104P0A0100 |
| 元件分類(lèi)： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 8.2 MHz, MICROCONTROLLER, PBGA240 |
| 封裝： | VFBGA10H-216 |
| 文件頁(yè)數(shù)： | 211/211頁(yè) |
| 文件大?。?/td> | 1802K |
| 代理商： | S1C88104P0A0100 |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)第120頁(yè)第121頁(yè)第122頁(yè)第123頁(yè)第124頁(yè)第125頁(yè)第126頁(yè)第127頁(yè)第128頁(yè)第129頁(yè)第130頁(yè)第131頁(yè)第132頁(yè)第133頁(yè)第134頁(yè)第135頁(yè)第136頁(yè)第137頁(yè)第138頁(yè)第139頁(yè)第140頁(yè)第141頁(yè)第142頁(yè)第143頁(yè)第144頁(yè)第145頁(yè)第146頁(yè)第147頁(yè)第148頁(yè)第149頁(yè)第150頁(yè)第151頁(yè)第152頁(yè)第153頁(yè)第154頁(yè)第155頁(yè)第156頁(yè)第157頁(yè)第158頁(yè)第159頁(yè)第160頁(yè)第161頁(yè)第162頁(yè)第163頁(yè)第164頁(yè)第165頁(yè)第166頁(yè)第167頁(yè)第168頁(yè)第169頁(yè)第170頁(yè)第171頁(yè)第172頁(yè)第173頁(yè)第174頁(yè)第175頁(yè)第176頁(yè)第177頁(yè)第178頁(yè)第179頁(yè)第180頁(yè)第181頁(yè)第182頁(yè)第183頁(yè)第184頁(yè)第185頁(yè)第186頁(yè)第187頁(yè)第188頁(yè)第189頁(yè)第190頁(yè)第191頁(yè)第192頁(yè)第193頁(yè)第194頁(yè)第195頁(yè)第196頁(yè)第197頁(yè)第198頁(yè)第199頁(yè)第200頁(yè)第201頁(yè)第202頁(yè)第203頁(yè)第204頁(yè)第205頁(yè)第206頁(yè)第207頁(yè)第208頁(yè)第209頁(yè)第210頁(yè)當(dāng)前第211頁(yè)
S1C8F626 TECHNICAL MANUAL
EPSON
91
5 PERIPHERAL CIRCUITS AND THEIR OPERATION (Programmable Timer)
Compare data register
The programmable timer has a built-in data
comparator so that count data can be compared
with an optional value. The compare data register
(CDRx) is used to set the value to be compared.
In the 8-bit mode, CDRx is used as an 8-bit register
separated for each timer.
In the 16-bit mode, the CDR(L) register is handled
as low-order 8 bits of compare data, and the
CDR(H) register is as high-order 8 bits.
The compare data register can be read and written,
and all the registers are set to 00H at initial reset.
The programmable timer compares count data
with the compare data register (CDRx), and
generates a compare match signal when they
become the same value. This compare match signal
generates an interrupt, and controls the clock
(TOUTx signal) output.
Timer operation
Timer is equipped with PTRUNx register which
controls the RUN/STOP of the timer. Timer x
starts down counting by writing "1" to the
PTRUNx register. However, it is necessary to
control the input clock and to preset the reload
data before starting a count.
When "0" is written to PTRUNx register, clock
input is prohibited, and the count stops.
This RUN/STOP control does not affect data in the
counter. The data in the counter is maintained
during count deactivation, so it is possible to
resume counting from the data.
In the 8-bit mode, the timers can be controlled
individually by the PTRUNx register.
In the 16-bit mode, the PTRUN(L) register controls
a pair of timers as a 16-bit timer. In this case,
control of the PTRUN(H) register is invalid.
The buffers PTMx is attached to the counter, and
reading is possible in optional timing.
When the counter agrees with the data set in the
compare data register during down counting, the
timer generates a compare match interrupt.
And, when the counter underflows, an underflow
interrupt is generated, and the initial value set in
the reload data register is loaded to the counter.
The interrupt generated does not stop the down
counting.
After an underflow interrupt is generated, the
counter continues counting from the initial value
reloaded.
PTRUNx
PSETx
RDRx
CDRx
Input clock
PTMx7
PTMx6
PTMx5
PTMx4
PTMx3
PTMx2
PTMx1
PTMx0
A6H
58H
A6H
58H
F3H
Preset
Underflow interrupt
generation
Reload
1
Compare match
interrupt generation
Fig. 5.10.4.1 Basic operation timing of counter (an example of 8-bit mode)
Note: The programmable timer counts down at the falling edge of the input clock and at the same time it
generates an interrupt if the counter underflows. Then it starts loading the reload data to the counter
and the counter data is determined at the next rising edge of the input clock (period shown in as
1
in the figure).
To avoid improper reloading, do not rewrite the reload data after an interrupt occurs until the counter
data is determined including the reloading period
1. Be especially careful when using the OSC1
(low-speed clock) as the clock source of the programmable timer and the CPU is operating with the
OSC3 (high-speed clock).
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| S1C88317D0A0100 | MICROCONTROLLER, UUC170 |
| S1C88308D0A0100 | MICROCONTROLLER, UUC170 |
| S1C88308F0A0100 | MICROCONTROLLER, PQFP160 |
| S1C88348F | 8-BIT, MROM, 8.2 MHz, MICROCONTROLLER, PQFP16 |
| S1C88316D | 8-BIT, MROM, 8.2 MHz, MICROCONTROLLER, UUC172 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| S1C88349 | 制造商:EPSON 制造商全稱(chēng):EPSON 功能描述:8-bit Single Chip Microcomputer |
| S1C88649 | 制造商:EPSON 制造商全稱(chēng):EPSON 功能描述:8-bit Single Chip Microcomputer |
| S1C88650 | 制造商:EPSON 制造商全稱(chēng):EPSON 功能描述:8-bit Single Chip Microcomputer |
| S1C88655 | 制造商:EPSON 制造商全稱(chēng):EPSON 功能描述:8-bit Single Chip Microcomputer |
| S1C88816 | 制造商:EPSON 制造商全稱(chēng):EPSON 功能描述:8-bit Single Chip Microcomputer |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。