- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄98068 > S1C88104P0A0100 8-BIT, MROM, 8.2 MHz, MICROCONTROLLER, PBGA240 PDF資料下載
參數(shù)資料
| 型號(hào)： | S1C88104P0A0100 |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 8.2 MHz, MICROCONTROLLER, PBGA240 |
| 封裝： | VFBGA10H-216 |
| 文件頁(yè)數(shù)： | 192/211頁(yè) |
| 文件大小： | 1802K |
| 代理商： | S1C88104P0A0100 |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)第120頁(yè)第121頁(yè)第122頁(yè)第123頁(yè)第124頁(yè)第125頁(yè)第126頁(yè)第127頁(yè)第128頁(yè)第129頁(yè)第130頁(yè)第131頁(yè)第132頁(yè)第133頁(yè)第134頁(yè)第135頁(yè)第136頁(yè)第137頁(yè)第138頁(yè)第139頁(yè)第140頁(yè)第141頁(yè)第142頁(yè)第143頁(yè)第144頁(yè)第145頁(yè)第146頁(yè)第147頁(yè)第148頁(yè)第149頁(yè)第150頁(yè)第151頁(yè)第152頁(yè)第153頁(yè)第154頁(yè)第155頁(yè)第156頁(yè)第157頁(yè)第158頁(yè)第159頁(yè)第160頁(yè)第161頁(yè)第162頁(yè)第163頁(yè)第164頁(yè)第165頁(yè)第166頁(yè)第167頁(yè)第168頁(yè)第169頁(yè)第170頁(yè)第171頁(yè)第172頁(yè)第173頁(yè)第174頁(yè)第175頁(yè)第176頁(yè)第177頁(yè)第178頁(yè)第179頁(yè)第180頁(yè)第181頁(yè)第182頁(yè)第183頁(yè)第184頁(yè)第185頁(yè)第186頁(yè)第187頁(yè)第188頁(yè)第189頁(yè)第190頁(yè)第191頁(yè)當(dāng)前第192頁(yè)第193頁(yè)第194頁(yè)第195頁(yè)第196頁(yè)第197頁(yè)第198頁(yè)第199頁(yè)第200頁(yè)第201頁(yè)第202頁(yè)第203頁(yè)第204頁(yè)第205頁(yè)第206頁(yè)第207頁(yè)第208頁(yè)第209頁(yè)第210頁(yè)第211頁(yè)
S1C8F626 TECHNICAL MANUAL
EPSON
73
5 PERIPHERAL CIRCUITS AND THEIR OPERATION (Serial Interface)
TXTRG0: 00FF49HD1
TXTRG1: 00FF4DHD1
Functions as the transmitting start trigger and the
operation status indicator (transmitting/stop
status).
When "1" is read:
During transmitting
When "0" is read:
During stop
When "1" is written: Transmitting start
When "0" is written: Invalid
Starts the transmitting when "1" is written to
TXTRGx after writing the transmitting data.
TXTRGx can be read as the status. When set to "1",
it indicates transmitting operation, and "0" indicates
transmitting stop.
At initial reset, TXTRGx is set to "0" (during stop).
RXEN0: 00FF49HD2
RXEN1: 00FF4DHD2
Sets the serial interface to the receiving enable
status.
When "1" is written: Receiving enable
When "0" is written: Receiving disable
Reading:
Valid
When "1" is written to RXENx, the serial interface
shifts to the receiving enable status and shifts to the
receiving disable status when "0" is written.
Set RXENx to "0" when making the initial settings
of the serial interface and similar operations.
At initial reset, RXENx is set to "0" (receiving
disable).
RXTRG0: 00FF49HD3
RXTRG1: 00FF4DHD3
Functions as the receiving start trigger or prepara-
tion for the following data receiving and the
operation status indicator (during receiving/during
stop).
When "1" is read:
During receiving
When "0" is read:
During stop
When "1" is written: Receiving start/following
data receiving preparation
When "0" is written: Invalid
RXTRGx has a slightly different operation in the
clock synchronous system and the asynchronous
system.
The RXTRGx in the clock synchronous system, is
used as the trigger for the receiving start.
Writes "1" into RXTRGx to start receiving at the
point where the receive data has been read and the
following receive preparation has been done. (In
_________
the slave mode, SRDYx becomes "0" at the point
where "1" has been written into the RXTRGx.)
RXTRGx is used in the asynchronous system for
preparation of the following data receiving. Reads
the received data located in the received data buffer
and writes "1" into RXTRGx to inform that the
received data buffer has shifted to empty. When "1"
has not been written to RXTRGx, the overrun error
flag OERx is set to "1" at the point where the
following receiving has been completed. (When the
receiving has been completed between the opera-
tion to read the received data and the operation to
write "1" into RXTRGx, an overrun error occurs.)
In addition, RXTRGx can be read as the status. In
either clock synchronous mode or asynchronous
mode, when RXTRGx is set to "1", it indicates
receiving operation and when set to "0", it indicates
that receiving has stopped.
At initial reset, RXTRGx is set to "0" (during stop).
TRXD00–TRXD07: 00FF4AH
TRXD10–TRXD17: 00FF4EH
During transmitting
Write the transmitting data into the transmit shift
register.
When "1" is written: HIGH level
When "0" is written: LOW level
Write the transmitting data prior to starting
transmitting.
In the case of continuous transmitting, wait for the
transmitting complete interrupt, then write the
data.
The TRXDx7 becomes invalid for the asynchronous
7-bit mode.
Converted serial data for which the bits set at "1" as
HIGH (VDD) level and for which the bits set at "0"
as LOW (VSS) level are output from the SOUTx
terminal.
During receiving
Read the received data.
When "1" is read:
HIGH level
When "0" is read:
LOW level
The data from the received data buffer can be read
out.
Since the sift register is provided separately from
this buffer, reading can be done during the receive
operation in the asynchronous mode. (The buffer
function is not used in the clock synchronous
mode.)
Read the data after waiting for the receiving
complete interrupt.
When performing parity check in the asynchronous
7-bit mode, "0" is loaded into the 8th bit (TRXDx7)
that corresponds to the parity bit.
The serial data input from the SINx terminal is level
converted, making the HIGH (VDD) level bit "1" and
the LOW (VSS) level bit "0" and is then loaded into
this buffer.
At initial reset, the buffer content is undefined.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| S1C88317D0A0100 | MICROCONTROLLER, UUC170 |
| S1C88308D0A0100 | MICROCONTROLLER, UUC170 |
| S1C88308F0A0100 | MICROCONTROLLER, PQFP160 |
| S1C88348F | 8-BIT, MROM, 8.2 MHz, MICROCONTROLLER, PQFP16 |
| S1C88316D | 8-BIT, MROM, 8.2 MHz, MICROCONTROLLER, UUC172 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| S1C88349 | 制造商:EPSON 制造商全稱:EPSON 功能描述:8-bit Single Chip Microcomputer |
| S1C88649 | 制造商:EPSON 制造商全稱:EPSON 功能描述:8-bit Single Chip Microcomputer |
| S1C88650 | 制造商:EPSON 制造商全稱:EPSON 功能描述:8-bit Single Chip Microcomputer |
| S1C88655 | 制造商:EPSON 制造商全稱:EPSON 功能描述:8-bit Single Chip Microcomputer |
| S1C88816 | 制造商:EPSON 制造商全稱:EPSON 功能描述:8-bit Single Chip Microcomputer |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。