
S1C8F626 TECHNICAL MANUAL
EPSON
13
5 PERIPHERAL CIRCUITS AND THEIR OPERATION (I/O Memory Map)
5 PERIPHERAL CIRCUITS AND
THEIR OPERATION
The peripheral circuits of the S1C8F626 is interfaced with the CPU by means of the memory mapped
I/O method. For this reason, just as with other memory access operations, peripheral circuits can be
controlled by manipulating I/O memory. Below is a description of the operation and control method for
each individual peripheral circuit.
5.1 I/O Memory Map
Table 5.1.1(a) I/O Memory map (00FF00H–00FF10H)
SR R/W
10
Address Bit
Name
Function
Comment
00FF00 D7
D6
D5
D4
D3
D2
D1
D0
–
0
–
R/W
–
CPU mode
–
"0" when being read
Constantly "0" when
being read
–
Maximum
–
Minimum
–
CPUMOD
–
00FF01 D7
D6
D5
D4
D3
D2
D1
D0
SPP7
SPP6
SPP5
SPP4
SPP3
SPP2
SPP1
SPP0
0
R/W
0
Stack pointer page address
1
(MSB)
(LSB)
00FF02 D7
D6
D5
D4
D3
D2
D1
D0
–
CLKCHG
SOSC3
–
VDC
–
1
–
0
R/W
–
OSC3
On
–
VD1 = 2.5 V
–
OSC1
Off
–
VD1 = 1.8 V
–
CPU operating clock switch
OSC3 oscillation On/Off control
–
Operating mode selection
Constantly "0" when
being read
"0" when being read
00FF03 D7
D6
D5
D4
D3
D2
D1
D0
–
0
R/W
–
Power source select for LCD voltage regulator
Power voltage booster On/Off control
Constantly "0" when
being read
–
VD2
On
–
VDD
Off
–
VDSEL
DBON
00FF10 D7
D6
D5
D4
D3
D2
D1
D0
HLMOD
SEGREV
–
DTFNT
LDUTY1
LDUTY0
Heavy load protection mode
Reverse SEG assignment
R/W register
LCD dot font selection
LCD drive duty selection
Reserved register
0
1
0
R/W
On
Reverse
1
12
×12
Off
Normal
0
16
×16/5×8
LDUTY1
1
0
LDUTY0
1
0
1
0
Duty
Not allowed
1/16
1/32
1/8
Note:
____
All the interrupts including NMI are disabled, until you write the optional value into both the 00FF00H and
00FF01H addresses.