- 您現(xiàn)在的位置：買(mǎi)賣(mài)IC網(wǎng) > PDF目錄98068 > S1C88104P0A0100 8-BIT, MROM, 8.2 MHz, MICROCONTROLLER, PBGA240 PDF資料下載
參數(shù)資料
| 型號(hào)： | S1C88104P0A0100 |
| 元件分類(lèi)： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 8.2 MHz, MICROCONTROLLER, PBGA240 |
| 封裝： | VFBGA10H-216 |
| 文件頁(yè)數(shù)： | 210/211頁(yè) |
| 文件大?。?/td> | 1802K |
| 代理商： | S1C88104P0A0100 |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)第120頁(yè)第121頁(yè)第122頁(yè)第123頁(yè)第124頁(yè)第125頁(yè)第126頁(yè)第127頁(yè)第128頁(yè)第129頁(yè)第130頁(yè)第131頁(yè)第132頁(yè)第133頁(yè)第134頁(yè)第135頁(yè)第136頁(yè)第137頁(yè)第138頁(yè)第139頁(yè)第140頁(yè)第141頁(yè)第142頁(yè)第143頁(yè)第144頁(yè)第145頁(yè)第146頁(yè)第147頁(yè)第148頁(yè)第149頁(yè)第150頁(yè)第151頁(yè)第152頁(yè)第153頁(yè)第154頁(yè)第155頁(yè)第156頁(yè)第157頁(yè)第158頁(yè)第159頁(yè)第160頁(yè)第161頁(yè)第162頁(yè)第163頁(yè)第164頁(yè)第165頁(yè)第166頁(yè)第167頁(yè)第168頁(yè)第169頁(yè)第170頁(yè)第171頁(yè)第172頁(yè)第173頁(yè)第174頁(yè)第175頁(yè)第176頁(yè)第177頁(yè)第178頁(yè)第179頁(yè)第180頁(yè)第181頁(yè)第182頁(yè)第183頁(yè)第184頁(yè)第185頁(yè)第186頁(yè)第187頁(yè)第188頁(yè)第189頁(yè)第190頁(yè)第191頁(yè)第192頁(yè)第193頁(yè)第194頁(yè)第195頁(yè)第196頁(yè)第197頁(yè)第198頁(yè)第199頁(yè)第200頁(yè)第201頁(yè)第202頁(yè)第203頁(yè)第204頁(yè)第205頁(yè)第206頁(yè)第207頁(yè)第208頁(yè)第209頁(yè)當(dāng)前第210頁(yè)第211頁(yè)
90
EPSON
S1C8F626 TECHNICAL MANUAL
5 PERIPHERAL CIRCUITS AND THEIR OPERATION (Programmable Timer)
Table 5.10.3.2 Division ratio and control registers
(OSC1)
fOSC1/128
fOSC1/64
fOSC1/32
fOSC1/16
fOSC1/8
fOSC1/4
fOSC1/2
fOSC1/1
(OSC3)
fOSC3/4096
fOSC3/1024
fOSC3/256
fOSC3/64
fOSC3/32
fOSC3/8
fOSC3/2
fOSC3/1
PSTx2
1
0
Register
Dividing ratio
PSTx1
1
0
1
0
PSTx0
1
0
1
0
1
0
1
0
The set clock is output to Timer x by writing "1" to
the clock control register PRPRTx.
When the 16-bit mode is selected, the program-
mable timer operates with the clock input to
Timer(L), and Timer(H) inputs the Timer(L)
underflow signal as the clock. Therefore, the
setting of Timer(H) input clock is invalid.
5.10.4 Operation and control of timer
Reload data register and setting
of initial value
The reload data register (RDRx) is used to set an
initial value of the down counter.
In the 8-bit mode, RDRx is used as an 8-bit register
separated for each timer.
In the 16-bit mode, the RDR(L) register is handled
as low-order 8 bits of reload data, and the RDR(H)
register is as high-order 8 bits.
The reload data register can be read and written,
and all the registers are set to FFH at initial reset.
Data written in this register is loaded into the
down counter, and a down counting starts from
the value.
The down counter is preset, in the following two
cases:
1) When software presets
The software preset can be done using the
preset control bits PSETx corresponding to
Timer x. When the preset control bit is set to
"1", the content of the reload data register is
loaded into the down counter at that point.
In the 16-bit mode, a 16-bit reload data is
loaded all at one time by setting PSET(L). In
this case, writing to PSET(H) is invalid.
2) When down counter has underflowed during a count
Since the down counter presets the reload data
by the underflow, the underflow period is
decided according to the value set in the reload
data register. This underflow generates an
interrupt, and controls the clock (TOUTx
signal) output.
5.10.3 Setting of input clock
The clock to be input to the counter can be selected
from either the internal clock or external clock by
the input clock selection register (CKSEL) pro-
vided for each timer. The internal clock is an
output of the prescaler. The external clock is used
for the event counter function. A signal from the
input port is used as the count clock.
Table 5.10.3.1 shows the input clock selection
register and input clock of each timer.
Table 5.10.3.1 Input clock selection
Timer
Timer 0
Timer 1
Timer 2
Timer 3
Timer 4
Timer 5
Timer 6
Timer 7
Register setting
CKSEL0 = "0"
CKSEL0 = "1"
CKSEL1 = "0"
CKSEL1 = "1"
CKSEL2 = "0"
CKSEL2 = "1"
CKSEL3 = "0"
CKSEL3 = "1"
CKSEL4 = "0"
CKSEL4 = "1"
CKSEL5 = "0"
CKSEL5 = "1"
CKSEL6 = "0"
CKSEL6 = "1"
CKSEL7 = "0"
CKSEL7 = "1"
Input clock
INCL0 (Prescaler)
EXCL0 (K04 input)
INCL1 (Prescaler)
EXCL0 (K04 input)
INCL2 (Prescaler)
EXCL1 (K05 input)
INCL3 (Prescaler)
EXCL1 (K05 input)
INCL4 (Prescaler)
EXCL2 (K06 input)
INCL5 (Prescaler)
EXCL2 (K06 input)
INCL6 (Prescaler)
EXCL3 (K07 input)
INCL7 (Prescaler)
EXCL3 (K07 input)
When the external clock is selected, a signal from
the input port is input to the programmable timer.
An noise rejector is incorporated in the external
clock input circuit and it can be enabled/disabled
using the external clock noise rejector select
registers PTNREN_A through PTNREN_D corre-
sponding to the EXCL0 through EXCL3 inputs.
Writing "1" to PTNREN_A (–D) enables the noise
rejector for the external clock EXCL0 (–3). The
noise rejector regards pulses less than a 16/fOSC1
seconds in width as noise and rejects them (an
external clock must have a pulse width at least
double the rejected width). When PTNREN_A (–D)
is "0", the external clock bypasses the noise rejector.
When the internal clock is used, select a source
clock and a division ratio of the prescaler to set the
clock frequency for each timer.
The source clock is specified using the source clock
selection register PRTFx provided for each timer.
When "1" is written to PRTFx, the OSC1 clock is
selected as the source clock for Timer x. When "0"
is written, the OSC3 clock is selected. The OSC3
oscillation circuit must be on before the OSC3 can
be used. See "5.4 Oscillation Circuits and
Operating Mode" for the controlling of the OSC3
oscillation circuit.
The prescaler provides the division ratio selection
register PSTx0–PSTx2 for each timer. Note that the
division ratio varies depending on the selected
source clock.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| S1C88317D0A0100 | MICROCONTROLLER, UUC170 |
| S1C88308D0A0100 | MICROCONTROLLER, UUC170 |
| S1C88308F0A0100 | MICROCONTROLLER, PQFP160 |
| S1C88348F | 8-BIT, MROM, 8.2 MHz, MICROCONTROLLER, PQFP16 |
| S1C88316D | 8-BIT, MROM, 8.2 MHz, MICROCONTROLLER, UUC172 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| S1C88349 | 制造商:EPSON 制造商全稱:EPSON 功能描述:8-bit Single Chip Microcomputer |
| S1C88649 | 制造商:EPSON 制造商全稱:EPSON 功能描述:8-bit Single Chip Microcomputer |
| S1C88650 | 制造商:EPSON 制造商全稱:EPSON 功能描述:8-bit Single Chip Microcomputer |
| S1C88655 | 制造商:EPSON 制造商全稱:EPSON 功能描述:8-bit Single Chip Microcomputer |
| S1C88816 | 制造商:EPSON 制造商全稱:EPSON 功能描述:8-bit Single Chip Microcomputer |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。