參數(shù)資料
型號： S1C63653F
元件分類： 微控制器/微處理器
英文描述： 4-BIT, FLASH, 4 MHz, MICROCONTROLLER, CQFP100
封裝： CERAMIC, QFP15-100
文件頁數(shù)： 58/121頁
文件大?。?/td> 1127K
代理商： S1C63653F
S1C63653 TECHNICAL MANUAL
EPSON
33
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Oscillation Circuit)
4.4.6 I/O memory of oscillation circuit
Table 4.4.6.1 shows the I/O address and the control bits for the oscillation circuit.
Table 4.4.6.1 Control bits of oscillation circuit
Address
Comment
D3
D2
Register
D1
D0
Name
Init 1
10
FF01H
CLKCHG OSCC
0
R/W
R
CLKCHG
OSCC
0 3
0
– 2
OSC3
On
OSC1
Off
CPU clock switch
OSC3 oscillation On/Off
Unused
FF00H
VDC3
VDC2
VDC1
VDC0
R/W
VDC3
VDC2
VDC1
VDC0
0
1/2VDD
On
VD3
VDD
Off
VD1L
LCD system voltage regulator power source switch
Low-speed operation voltage regulator power source switch
High-speed operation voltage regulator on/off
Logic system power source switch
*1 Initial value at initial reset
*2 Not set in the circuit
*3 Constantly "0" when being read
VDC0: Internal logic system power switching register (FF00HD0)
It is used to switch the operating voltage for the CPU and internal circuit.
When "1" is written: VD3
(for OSC3 operation)
When "0" is written: VD1L
(for OSC1 operation)
Reading: Valid
When "1" is written to VDC0, the internal operating voltage is switched to VD3. After switching to VD3,
the OSC3 oscillation can be started.
When the low-speed operation voltage regulator is in the halver mode, return it to the normal mode
before switching to VD3.
When "0" is written to VDC0, the internal operating voltage is switched to VD1L. Stop the OSC3 oscillation
before switching to VD1L.
At initial reset, this register is set to "0".
OSCC: OSC3 oscillation control register (FF01HD2)
Turns the OSC3 oscillation circuit on and off.
When "1" is written: OSC3 oscillation On
When "0" is written: OSC3 oscillation Off
Reading: Valid
When it is necessary to operate the CPU at high speed, set OSCC to "1". At other times, set it to "0" to
reduce current consumption. Furthermore, it is necessary to switch the operating voltage when turning
the OSC3 oscillation circuit on and off.
At initial reset, this register is set to "0".
CLKCHG: CPU system clock switching register (FF01HD3)
The CPU's operation clock is selected with this register.
When "1" is written: OSC3 clock is selected
When "0" is written: OSC1 clock is selected
Reading: Valid
When the CPU clock is to be OSC3, set CLKCHG to "1"; for OSC1, set CLKCHG to "0".
After turning the OSC3 oscillation on (OSCC = "1"), switching of the clock should be done after waiting 5
msec or more.
When VDC0 = "0" and OSCC = "0" (OSC3 oscillation is off), setting of CLKCHG = "1" becomes invalid
and switching to OSC3 is not performed. Furthermore, do not switch the CPU clock to OSC3 in the halver
mode.
At initial reset, this register is set to "0".
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