- 您現(xiàn)在的位置：買(mǎi)賣(mài)IC網(wǎng) > PDF目錄98068 > S1C63653F 4-BIT, FLASH, 4 MHz, MICROCONTROLLER, CQFP100 PDF資料下載
參數(shù)資料
| 型號(hào)： | S1C63653F |
| 元件分類(lèi)： | 微控制器/微處理器 |
| 英文描述： | 4-BIT, FLASH, 4 MHz, MICROCONTROLLER, CQFP100 |
| 封裝： | CERAMIC, QFP15-100 |
| 文件頁(yè)數(shù)： | 16/121頁(yè) |
| 文件大?。?/td> | 1127K |
| 代理商： | S1C63653F |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)當(dāng)前第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)第120頁(yè)第121頁(yè)
104
EPSON
S1C63653 TECHNICAL MANUAL
CHAPTER 5: SUMMARY OF NOTES
5.2 Summary of Notes by Function
Here, the cautionary notes are summed up by function category. Keep these notes well in mind when
programming.
Memory and stack
(1)Memory is not implemented in unused areas within the memory map. Further, some non-implemen-
tation areas and unused (access prohibition) areas exist in the peripheral I/O area. If the program that
accesses these areas is generated, its operation cannot be guaranteed. Refer to the I/O memory maps
shown in Table 4.1.1 for the peripheral I/O area.
(2) Part of the RAM area is used as a stack area for subroutine call and register evacuation, so pay
attention not to overlap the data area and stack area.
(3) The S1C63000 core CPU handles the stack using the stack pointer for 4-bit data (SP2) and the stack
pointer for 16-bit data (SP1).
16-bit data are accessed in stack handling by SP1, therefore, this stack area should be allocated to the
area where 4-bit/16-bit access is possible (0100H to 01FFH). The stack pointers SP1 and SP2 change
cyclically within their respective range: the range of SP1 is 0000H to 03FFH and the range of SP2 is
0000H to 00FFH. Therefore, pay attention to the SP1 value because it may be set to 0200H or more
exceeding the 4-bit/16-bit accessible range in the S1C63653 or it may be set to 00FFH or less. Memory
accesses except for stack operations by SP1 are 4-bit data access. After initial reset, all the interrupts
including NMI are masked until both the stack pointers SP1 and SP2 are set by software. Further, if
either SP1 or SP2 is re-set when both are set already, the interrupts including NMI are masked again
until the other is re-set. Therefore, the settings of SP1 and SP2 must be done as a pair.
Power control
(1) When setting the low-speed operation voltage regulator into the halver mode, switch the CPU clock to
OSC1 before writing "1" to VDC2.
(2) When setting the LCD system voltage circuit into the halver mode, set the VC1 voltage (contrast) to
1.13 V or lower (LC register = 6 or less) before writing "1" to VDC3.
Watchdog timer
(1) When the watchdog timer is being used, the software must reset it within 3-second cycles.
(2) Because the watchdog timer is set in operation state by initial reset, set the watchdog timer to disabled
state (not used) before generating an interrupt (NMI) if it is not used.
Oscillation circuit
(1) When switching the CPU system clock from OSC1 to OSC3, first set the operating voltage for high-
speed operation (VD3). After that maintain 2.5 msec or more, and then turn the OSC3 oscillation on.
When switching from OSC3 to OSC1, set the operating voltage for low-speed operation (VD1L) after
switching to OSC1 and turning the OSC3 oscillation off.
(2) It takes at least 5 msec from the time the OSC3 oscillation circuit goes on until the oscillation stabi-
lizes. Consequently, when switching the CPU operation clock from OSC1 to OSC3, do this after a
minimum of 5 msec have elapsed since the OSC3 oscillation went on.
Further, the oscillation stabilization time varies depending on the external oscillator characteristics
and conditions of use, so allow ample margin when setting the wait time.
(3) When switching the clock form OSC3 to OSC1, use a separate instruction for switching the OSC3
oscillation off. An error in the CPU operation can result if this processing is performed at the same
time by the one instruction.
(4) When the low-speed operation voltage regulator is in the halver mode (VDC2 = "1"), the system can
be operated only in low-speed using the OSC1 clock. Do not switch the system clock to OSC3.
(5) Do not switch the operating voltage to VD1L while the CPU is operating with the OSC3 clock. Further-
more, do not stop the high-speed operating voltage regulator.
(6) When selecting OSC3 for the time base counter clock of the R/f converter, the maximum frequency of
the OSC3 clock is limited to 2 MHz.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| S1C6F567D0A0100 | MICROCONTROLLER, UUC141 |
| S1C6N3B0D0A0100 | MICROCONTROLLER, UUC54 |
| S1C6P366D0A0100 | 4-BIT, FLASH, 4.1 MHz, MICROCONTROLLER, UUC102 |
| S1C6P466D0A0A00 | MICROCONTROLLER, UUC140 |
| S1C6S2L7D | 4-BIT, MROM, 0.032 MHz, MICROCONTROLLER, UUC58 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| S1C63656 | 制造商:EPSON 制造商全稱(chēng):EPSON 功能描述:4-bit Single Chip Microcomputer |
| S1C63657 | 制造商:EPSON 制造商全稱(chēng):EPSON 功能描述:CMOS 4-bit Single Chip Microcontroller |
| S1C63658 | 制造商:EPSON 制造商全稱(chēng):EPSON 功能描述:4-bit Single Chip Microcomputer |
| S1C63666 | 制造商:EPSON 制造商全稱(chēng):EPSON 功能描述:4-bit Single Chip Microcomputer |
| S1C63709 | 制造商:EPSON 制造商全稱(chēng):EPSON 功能描述:4-bit Single Chip Microcomputer |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。