參數(shù)資料
型號(hào)： S1C63653F
元件分類(lèi)： 微控制器/微處理器
英文描述： 4-BIT, FLASH, 4 MHz, MICROCONTROLLER, CQFP100
封裝： CERAMIC, QFP15-100
文件頁(yè)數(shù)： 110/121頁(yè)
文件大?。?/td> 1127K
代理商： S1C63653F
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S1C63653 TECHNICAL MANUAL
EPSON
81
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Sound Generator)
4.11.6 I/O memory of sound generator
Table 4.11.6.1 shows the I/O addresses and the control bits for the sound generator.
Table 4.11.6.1 Control bits of sound generator
Address
Comment
D3
D2
Register
D1
D0
Name
Init 1
10
0
4096.0
1
3276.8
2
2730.7
3
2340.6
[BZFQ2, 1, 0]
Frequency (Hz)
4
2048.0
5
1638.4
6
1365.3
7
1170.3
[BZFQ2, 1, 0]
Frequency (Hz)
FF6EH
0
BZFQ2
BZFQ1
BZFQ0
RR/W
0 3
BZFQ2
BZFQ1
BZFQ0
– 2
0
Unused
Buzzer
frequency
selection
FF6FH
0
BDTY2
BDTY1
BDTY0
RR/W
0 3
BDTY2
BDTY1
BDTY0
– 2
0
Unused
Buzzer signal duty ratio selection
(refer to main manual)
FF6CH
ENRTM ENRST
ENON
BZE
R/W
W
R/W
ENRTM
ENRST3
ENON
BZE
0
Reset
0
1 sec
Reset
On
Enable
0.5 sec
Invalid
Off
Disable
Envelope releasing time
Envelope reset (writing)
Envelope On/Off
Buzzer output enable
FF6DH
0
BZSTP BZSHT SHTPW
RW
R/W
0 3
BZSTP3
BZSHT
SHTPW
– 2
0
Stop
Trigger
Busy
125 msec
Invalid
Ready
31.25 msec
Unused
1-shot buzzer stop (writing)
1-shot buzzer trigger (writing)
1-shot buzzer status (reading)
1-shot buzzer pulse width setting
*1 Initial value at initial reset
*2 Not set in the circuit
*3 Constantly "0" when being read
BZE: Buzzer output control register (FF6CHD0)
Controls the buzzer signal output.
When "1" is written: Buzzer output On
When "0" is written: Buzzer output Off
Reading: Valid
When "1" is written to BZE, the BZ signal is output from the BZ terminal.
When "0" is written, the BZ terminal goes to low (VSS).
At initial reset, this register is set to "0".
BZFQ0–BZFQ2: Buzzer frequency selection register (FF6EHD0–D2)
Selects the buzzer signal frequency.
Table 4.11.6.2 Buzzer signal frequency setting
Buzzer frequency (Hz)
4096.0
3276.8
2730.7
2340.6
2048.0
1638.4
1365.3
1170.3
BZFQ0
0
1
0
1
0
1
0
1
BZFQ1
0
1
0
1
BZFQ2
0
1
Select the buzzer frequency from among the above 8 types that have divided the oscillation clock.
At initial reset, this register is set to "0".
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