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參數(shù)資料
| 型號： | S1C63653F |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 4-BIT, FLASH, 4 MHz, MICROCONTROLLER, CQFP100 |
| 封裝： | CERAMIC, QFP15-100 |
| 文件頁數(shù)： | 19/121頁 |
| 文件大?。?/td> | 1127K |
| 代理商： | S1C63653F |
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S1C63653 TECHNICAL MANUAL
EPSON
107
CHAPTER 5: SUMMARY OF NOTES
(2) When an interrupt occurs by the counter overflow, the same interrupt will occur if the overflow flag
(OVMC or OVTBC) is not reset. Be sure to check and reset to "0" (writing "1") the overflow flag when
the R/f converter interrupt occurs.
(3) When selecting OSC3 for the time base counter clock, the maximum frequency of the OSC3 clock is
limited to 2 MHz.
(4) When setting the measurement counter, always write 5 words of data continuously in order from the
lower address (FF92H
→ FF93H → FF94H → FF95H → FF96H). Furthermore, an LD instruction
should be used for writing data to the measurement counter and a read-modify-write instruction
(AND, OR, ADD, SUB, etc.) cannot be used.
Interrupt
(1) The interrupt factor flags are set when the interrupt condition is established, even if the interrupt
mask registers are set to "0".
(2) After an interrupt occurs, the same interrupt will occur again if the interrupt enabled state (I flag =
"1") is set or the RETI instruction is executed unless the interrupt factor flag is reset. Therefore, be sure
to reset (write "1" to) the interrupt factor flag in the interrupt service routine before shifting to the
interrupt enabled state.
(3) After an initial reset, all the interrupts including NMI are masked until both the stack pointers SP1
and SP2 are set with the software. Be sure to set the SP1 and SP2 in the initialize routine.
Further, when re-setting the stack pointer, the SP1 and SP2 must be set as a pair. When one of them is
set, all the interrupts including NMI are masked and interrupts cannot be accepted until the other one
is set.
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