
10.5 Digital Timing Characteristics
RTL8208
2001/01/07
37
Rev.1.923
Parameter
SYM
Conditions
Min
Typical
Max
Units
100Base-TX Transmit System Timing
Active TX_EN Sampled to
first bit of “J on MDI output
Inactive TX_EN Sampled
to first bit of “T on MDI
output
TX Propagation Delay
11
12
Bits
15
16
Bits
t
TXpd
From TXD[1:0] to TXOP/N
100Base-TX Receive System Timing
From RXIP/N to CRS_DV
11
12
Bits
First bit of “J on MDI input
to CRS_DV assert
First bit of “T on MDI input
to CRS_DV de-assert
RX Propagation Delay
6
8
Bits
From RXIP/N to CRS_DV
16
18
Bits
t
RXpd
From RXIP/N to RXD[1:0]
10Base-T Transmit System Timing
t
TXpd
From TXD[1:0] to TXOP/N
From TX_EN assert to TXOP/N
10Base-T Receive System Timing
15
17
Bits
TX Propagation Delay
TX_EN to MDI output
5
5
6
6
Bits
Bits
Carrier Sense Turn-on delay t
CSON
Preamble on RXIP/N to CRS_DV asserted
Carrier Sense Turn-off
Delay
RX Propagation Delay
t
RXpd
From RXIP/N to RXD[1:0]
12
8
Bits
Bits
t
CSOFF
TP_IDL to CRS_DV de-asserted
9
9
12
Bits
LED timing
LED On Time
LED Off Time
t
LEDon
While LED blinking
t
LEDoff
While LED blinking
43
43
120
120
ms
ms
Jabber timing (10Base-T only)
From TX_EN=1 to Jabber asserted
From TX_EN=0 to Jabber de-asserted
RMII Timing
TXD [1:0], TX_EN to REFCLK rising edge
setup time
TXD [1:0], TX_EN to REFCLK rising edge hold
time
Output delay from REFCLK rising edge to RXD
[1:0], CRSDV, RXER
SMII Timing
TXD, SYNC to REFCLK rising edge setup time
TXD SYNC to REFCLK rising edge hold time
Output delay from REFCLK rising edge to RXD
SMI Timing
MDC clock rate
Write cycle
Write cycle
Read cycle
Jabber Active
Jabber de-assert
60
60
70
80
80
ms
ms
TXD, TX_EN Setup time
2
ns
TXD, TX_EN Hold time
2
ns
RXD, CRSDV, RXER to
REFCLK delay
4
ns
TXD, SYNC Setup time
TXD, SYNC Hold time
RXD, to REFCLK delay
2
2
2.5
ns
ns
ns
3.5
MDC
25
10
10
MHz
ns
ns
ns
MDIO Setup Time
MDIO Hold Time
MDIO output delay relative
to rising edge of MDC
10