參數(shù)資料
型號: RTL8208
廠商: Electronic Theatre Controls, Inc.
英文描述: REALTEK SINGLE CHIP OCTAL 10/100 MBPS FAST ETHERNET TRANSCEIVER
中文描述: 瑞昱單芯片八路10/100 Mbps快速以太網(wǎng)收發(fā)器
文件頁數(shù): 24/40頁
文件大?。?/td> 546K
代理商: RTL8208
RTL8208
2001/01/07
24
Rev.1.923
7.5.3 Link Monitor
In 100Base-FX mode, if the RTL8208 receive path detects a valid link word, it enters the link state. If no valid link word is
detected, it is in a link down state. Therefore, SD+/- is not necessary. The RTL8208 uses a reduced 100Base-FX interface.
7.5.4 Far-End-Fault-Indication (FEFI)
The MII Register 1.4 (Remote Fault indication detected) is a FEFI bit when 100FX is enabled, which indicates FEFI has been
detected. FEFI is an alternative in-band signaling method which is composed of 84 consecutive ‘1’ followed by one ‘0’. From
the point of view of the RTL8208, once this pattern is detected 3 times, Register 1.4 is set, which means the transmit path
(Remote side’s receive path) has some problems.
On the other hand, if the RTL8208 detects no valid link pulse on RxOP/N pair, it sends out a FEFI stream pattern, which in turn
will cause the remote side to detect a Far-End-Fault indication. This means the RTL8208 sees problems on the receive path.
The FEFI mechanism is used only in 100Base-FX applications.
7.6 RMII/SMII/SS-SMII
The interface to the MAC can be RMII, SMII, or SS-SMII through MODE[1:0]. When floating MODE[1:0] upon power-on reset,
the RTL8208 operates in RMII mode (default).
MODE[1:0]
2’b1x
2’b00
2’b01
Operation Mode
RMII
SMII
SS-SMII
REFCLK Clock input
50MHz, 100ppm
125MHz, 100ppm
125MHz, 100ppm
Below illustrates the signals required for each interface:
RMII
SMII
SS-SMII
REFCLK
CRS_DV[3:0]
CRS_DV[4]
CRS_DV[7:5]
RXD0[7:0]
RXD1[7:0]
TX_EN[3:0]
TX_EN[4]
TX_EN[7:5]
TXD0[7:0]
TXD1[7:0]
REFCLK
SYNC
RXD0[7:0]
TXD0[7:0]
REFCLK
TX_SYNC
RX_SYNC
RX_CLK
RXD0[7:0]
TX_CLK
TXD0[7:0]
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