
8. Design and Layout Guide
RTL8208
2001/01/07
32
Rev.1.923
In order to achieve maximum performance for the RTL8208, good design attention is required throughout the design and layout
process. The following recommendations can help to implement a high performance system.
8.1 General Guidelines
Create a good power source, minimizing noise from switching power supply circuits.
Verify the quality of the components, such as clock source and transformer, to meet the application requirements.
Keep power and ground noise levels below 150mV.
Use bulk capacitors (4.7uF-10uF) between the power and ground planes.
Use 0.1uF decoupling capacitors to reduce high-frequency noise on the power and ground planes.
Keep decoupling capacitors as close as possible to the RTL8208 power pins.
Provide termination for all TXOP/N and RXIP/N.
8.2 Differential Signal Layout Guidelines
Keep differential pairs as close as possible and route both traces as identically as possible.
Avoid vias and layer changes if possible.
Keep the different pairs away from each other.
8.3 Clock Circuit
The clock should be 25M/50MHz/125MHz 100ppm with jitter less than 0.5ns.
If use 50MHz or 125MHz as clock source, make the length of clock path to RTL8208 equal to the length to MAC as possible.
The length difference should under 1 inch.
If use 50MHz, please put a damping resistor at clock source side.
If possible, make clock trace smooth, strait, and surrounded by ground traces to minimize high-frequency emissions.
8.4 2.5V power
Do not connect a bead directly between the collector of the PNP transistor and VDDAL. This will affects the stability of the
2.5V power significantly if a bead exists.
Use a bulk of capacitor (4.7uF-10uF) between the collector of PNP transistor and ground plane.
Do not use one PNP transistor for more than one RTL8208 chip, even if the rating is enough. Use one transistor for each
RTL8208.
8.5 Power Planes
If the layout board size is small, it is better not to divide the power plane into digital and analog power planes.
Use 0.1uF decoupling capacitors and bulk capacitors between power plane and ground plane.
8.6 Ground Planes
If the layout board size is small, keep the system ground region as one continuous, unbroken plane.
Place a moat (gap) between the system ground and chassis ground.
For better ESD test performance, please use iron case, and put screw to connect frame ground to iron case.
8.7 Transformer Options
The magnetics support 1:1 turn ratio on both the transmit and receive paths are valid for RTL8208. There are many vendors
improving their magnetics design to meet this requirement, and several are listed below.
Vendor
Model
Pulse
H1164
Magnetic 1
ML164
The center-tap of the primary side of the transformer should not be connected to ground with capacitors, because of the
RTL8208’s special design.
Vendor
BothHand
GTS
Model
40ST1041AX
FC-638L