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參數(shù)資料
| 型號： | RTL8208 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | REALTEK SINGLE CHIP OCTAL 10/100 MBPS FAST ETHERNET TRANSCEIVER |
| 中文描述： | 瑞昱單芯片八路10/100 Mbps快速以太網(wǎng)收發(fā)器 |
| 文件頁數(shù)： | 27/40頁 |
| 文件大小： | 546K |
| 代理商： | RTL8208 |
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RTL8208
2001/01/07
27
Rev.1.923
7.5.3 SS-SMII (Source Synchronous -Serial MII)
Source-Synchronous SMII is designed for applications requiring a trace delay of more than 1ns. Three signals are added to the
SMII interface: RX_SYNC, RX_CLK, TX_CLK; and the SYNC of SMII is modified to TX_SYNC in SS-SMII.
8-port
MAC
RTL8208
TX_SYNC
TXD0[7:0]
TX_CLK
RX_SYNC
RXD0[7:0]
RX_CLK
125MHz
oscillator
REFCLK
X1
SS-SMII Signal Diagram
Receive Path
Receive data and control information are signaled in 10-bit segments. RX_SYNC signal is used to delimit the 10-bit segments.
RTL8208 is responsible to generate these RX_SYNC pulses every ten clocks. For 100Mbps mode, each segment represents a
byte of data. However, for 10Mbps mode, each segment is repeated ten times to represent a byte of data. The receive sequence
contains all of the information defined on the standard MII receive path.
RX_CLK
RXD[0]
RX_SYNC
1 2 3 4 5 6 7 8 9 10
CRS
RXDV
RXD0
RXD7
RXD6
RXD5
RXD4
RXD3
RXD2
RXD1
SS-SMII Reception
Transmit Path
Transmit data and control information are signaled in 10-bit segments. TX_SYNC signal is used to delimit the 10-bit segments.
MAC is responsible to generate these TX_SYNC pulses every ten clocks. For 100Mbps mode, each segment represents a byte of
data. However, for 10Mbps mode, each segment is repeated ten times to represent a byte of data. The receive sequence contains
all of the information defined on the standard MII receive path. The PHY can sample one of the ten segments.
TX_CLK
TXD[0]
TX_SYNC
TX_ER
TX_EN
TXD0
TXD7
TXD6
TXD5
TXD4
TXD3
TXD2
TXD1
1 2 3 4 5 6 7 8 9 10
SS-SMII Transmission
Collision Detection
The RTL8208 does not indicate that a collision has occurred. It is left up to the MAC to detect the assertion of both CRS_DV and
TX_EN.
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