參數(shù)資料
型號(hào)： RTL8139D(L)
英文描述： RTL8139D(L) Specification
中文描述： RTL8139D（長(zhǎng)）規(guī)格
文件頁(yè)數(shù)： 33/58頁(yè)
文件大?。?/td> 616K
代理商： RTL8139D(L)
RTL8100B(L)
2001-11-9
Rev.1.41
33
Do not change this field without Realtek approval.
Bit7-3: Reserved.
Bit2: Link Down Power Saving mode:
Set to 1: Disable.
Set to 0: Enable. When cable is disconnected(Link Down), the analog part will power
down itself (PHY Tx part & part of twister) automatically except PHY Rx part and
part of twister to monitor SD signal in case that cable is re-connected and Link should
be established again.
Bit1: LANWake signal Enable/Disable
Set to 1: Enable LANWake signal.
Set to 0: Disable LANWake signal.
Bit0: PME_Status bit property
Set to 1: The PME_Status bit can be reset by PCI reset or by software if
D3cold_support_PME is 0. If D3cold_support_PME=1, the PME_Status bit is a
sticky bit.
Set to 0: The PME_Status bit is always a sticky bit and can only be reset by software.
Reserved. Do not change this field without Realtek approval.
Twister Parameter U for RTL8100B(L). Operational registers of the RTL8100B(L) are
7Ch-7Fh.
Reserved. Do not change this field without Realtek approval.
Twister Parameter T for RTL8100B(L). Operational registers of the RTL8100B(L) are
7Ch-7Fh.
PHY1_PARM_T Reserved. Do not change this field without Realtek approval.
PHY Parameter 1-T for RTL8100B(L). Operational registers of the RTL8100B(L) are
from 78h to 7Bh.
PHY2_PARM_T Reserved. Do not change this field without Realtek approval.
PHY Parameter 2-T for RTL8100B(L). Operational register of the RTL8100B(L) is 80h.
-
Reserved.
CheckSum
Reserved. Do not change this field without Realtek approval.
Checksum of the EEPROM content.
-
Reserved. Do not change this field without Realtek approval.
PXE_Para
Reserved. Do not change this field without Realtek approval.
PXE ROM code parameter.
VPD_Data
VPD data field. Offset 40h is the start address of the VPD data.
1Fh
CONFIG_5
20h-23h
TW_PARM_U
24h-27h
TW_PARM_T
28h-2Bh
2Ch
2Dh-31h
32h-33h
34h-3Eh
3Fh
40h-7Fh
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