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參數(shù)資料
| 型號： | RTL8139D(L) |
| 英文描述： | RTL8139D(L) Specification |
| 中文描述： | RTL8139D（長）規(guī)格 |
| 文件頁數(shù)： | 20/58頁 |
| 文件大?。?/td> | 616K |
| 代理商： | RTL8139D(L) |
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RTL8100B(L)
2001-11-9
Rev.1.41
20
5.10 CONFIG 0: Configuration Register 0
(Offset 0051h, R/W)
Bit
7
6
5
4-3
2-0
R/W
R
R
R
R
-
Symbol
SCR
PCS
T10
PL1, PL0
-
Description
Scrambler Mode:
Always 0.
PCS Mode:
Always 0.
10 Mbps Mode:
Always 0.
Select 10 Mbps medium type:
Always (PL1, PL0) = (1, 0)
Reserved
5.11 CONFIG 1: Configuration Register 1
(Offset 0052h, R/W)
Bit
7-6
5
R/W
R/W
R/W
Symbol
LEDS1-0
DVRLOAD
Description
Refer to the LED PIN definition. The initial value of these bits comes from the 93C46.
Driver Load:
Software may use this bit to make sure that the driver has been
loaded. Writing 1 is 1. Writing 0 is 0. When the command register bits IOEN,
MEMEN, and BMEN of the PCI configuration space are written, the
RTL8100B(L) will clear this bit automatically.
LWAKE active mode:
The LWACT bit and LWPTN bit in CONFIG4 register
are used to program the LWAKE pin’s output signal. According to the
combination of these two bits, there may be 4 choices of LWAKE signal, i.e.,
active high, active low, positive (high) pulse, and negative (low) pulse. The
output pulse width is about 150 ms.
The default value of each of these two bits is 0, i.e., the default output signal of
LWAKE pin is an active high signal.
0
Active high*
LWPTN
1
Positive pulse
* Default value.
Memory Mapping:
The operational registers are mapped into PCI memory space.
I/O Mapping:
The operational registers are mapped into PCI I/O space.
Set to enable Vital Product Data:
The VPD data is stored in 93C46 from within
offset 40h-7Fh.
Power Management Enable:
Writable only when 93C46CR register EEM1=EEM0=1
Let A denote the New_Cap bit (bit 4 of the Status Register) in the PCI
Configuration space offset 06H.
Let B denote the Cap_Ptr register in the PCI Configuration space offset 34H.
Let C denote the Cap_ID (power management) register in the PCI Configuration
space offset 50H.
Let D denote the power management registers in the PCI Configuration space
offset from 52H to 57H.
Let E denote the Next_Ptr (power management) register in the PCI
Configuration space offset 51H.
LWACT
LWAKE output
0
1
Active low
Negative pulse
4
R/W
LWACT
3
2
1
R
R
MEMMAP
IOMAP
VPD
R/W
0
R/W
PMEn
PMEn Description
1 A=1, B=50h, C=01h, D valid, E=0
0 A=B=C=E=0, D not valid
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