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參數(shù)資料
| 型號(hào)： | RTL8139D(L) |
| 英文描述： | RTL8139D(L) Specification |
| 中文描述： | RTL8139D（長(zhǎng)）規(guī)格 |
| 文件頁(yè)數(shù)： | 16/58頁(yè) |
| 文件大?。?/td> | 616K |
| 代理商： | RTL8139D(L) |
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RTL8100B(L)
2001-11-9
Rev.1.41
16
5.7 Transmit Configuration Register
(Offset 0040h-0043h, R/W)
This register defines the Transmit Configuration for the RTL8100B(L). It controls such functions as Loopback, programmable
Interframe Gap, Fill and Drain Thresholds, and maximum DMA burst size.
Bit
31
30-26
R/W
-
R
Symbol
-
HWVERID_A
Description
Reserved
Hardware Version ID A:
RTL8139
RTL8139A
RTL8139A-G
RTL8139B
RTL8130
RTL8139C
RTL8100
RTL8100B/
8139D
RTL8139C+
RTL8101
Reserved
Interframe Gap Time:
This field allows the user to adjust the
interframe gap time below the standard: 9.6
μs for 10Mbps, 960 ns for
100Mbps. The time can be programmed from 9.6 μs to 8.4 μs (10Mbps)
and 960ns to 840ns (100Mbps). Note that any value other than (1, 1)
will violate the IEEE 802.3 standard.
The formula for the inter frame gap is:
10 Mbps
100 Mbps
Hardware Version ID B
Reserved
Loopback test:
There will be no packet on the TX+/- lines under the
Loopback test condition. The loopback function must be independent of
the link state.
00 : normal operation
01 : Reserved
10 : Reserved
11 : Loopback mode
Append CRC:
Setting to 1 means that there is no CRC appended at the
end of a packet. Setting to 0 means that there is CRC appended at the
end of a packet.
Reserved
Max DMA Burst Size per Tx DMA Burst:
This field sets the
maximum size of transmit DMA data bursts according to the following
table:
000 = 16 bytes
001 = 32 bytes
010 = 64 bytes
011 = 128 bytes
100 = 256 bytes
101 = 512 bytes
110 = 1024 bytes
111 = 2048 bytes
Bit30 Bit29 Bit28 Bit27 Bit26 Bit23 Bit22
1
1
0
0
1
1
1
0
1
1
1
0
1
1
1
1
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
0
0
0
1
0
0
1
0
1
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
0
0
1
1
1
1
0
1
Other combination
25-24
R/W
IFG1, 0
8.4μs + 0.4(IFG(1:0)) μs
840ns + 40(IFG(1:0)) ns
23-22
21-19
18, 17
R
-
HWVERID_B
-
LBK1, LBK0
R/W
16
R/W
CRC
15-11
10-8
-
-
R/W
MXDMA2, 1, 0
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