SAM4CM Series [DATASHEET]
Atmel-11203C-ATARM-SAM4CM32-SAM4CM16-SAM4CM8-Datasheet_06-Oct-14
480
26.3
Special Bus Granting Mechanism
The Bus Matrix provides some speculative bus granting techniques in order to anticipate access requests from
masters. This mechanism reduces latency at first access of a burst, or for a single transfer, as long as the slave is
free from any other master access. However, the technique does not provide any benefits if the slave is
continuously accessed by more than one master, since arbitration is pipelined and has no negative effect on the
slave bandwidth or access latency.
This bus granting mechanism sets a different default master for every slave.
At the end of the current access, if no other request is pending, the slave remains connected to its associated
default master. A slave can be associated with three kinds of default masters:
No default master
Last access master
Fixed default master
To change from one type of default master to another, the Bus Matrix user interface provides Slave Configuration
registers, one for every slave which set a default master for each slave. The Slave Configuration register contains
two fields to manage master selection: DEFMSTR_TYPE and FIXED_DEFMSTR. The 2-bit DEFMSTR_TYPE
field selects the default master type (no default, last access master, fixed default master), whereas the 4-bit
FIXED_DEFMSTR field selects a fixed default master provided that DEFMSTR_TYPE is set to fixed default
master. Refer to
Section 26.9.2 “Bus Matrix Slave Configuration Registers” on page 487
.
26.4
No Default Master
After the end of the current access, if no other request is pending, the slave is disconnected from all masters.
This configuration incurs one latency clock cycle for the first access of a burst after bus idle. Arbitration without the
default master may be used for masters that perform significant bursts or several transfers with no idle in between,
or if the slave bus bandwidth is widely used by one or more masters.
This configuration provides no benefit on access latency or bandwidth when reaching maximum slave bus
throughput regardless of the number of requesting masters.
26.5
Last Access Master
After the end of the current access, if no other request is pending, the slave remains connected to the last master
that performed an access request.
This allows the Bus Matrix to remove one latency cycle for the last master that accessed the slave. Other non-
privileged masters still get one latency clock cycle if they need to access the same slave. This technique is used
for masters that perform single accesses or short bursts with some idle cycles in between.
This configuration provides no benefit on access latency or bandwidth when reaching maximum slave bus
throughput whatever is the number of requesting masters.
26.6
Fixed Default Master
After the end of the current access, if no other request is pending, the slave connects to its fixed default master.
Unlike the last access master, the fixed default master does not change unless the user modifies it by software
(FIXED_DEFMSTR field of the related MATRIX_SCFG).
This allows the Bus Matrix arbiters to remove the one latency clock cycle for the fixed default master of the slave.
All requests attempted by the fixed default master do not cause any arbitration latency, whereas other non-
privileged masters will get one latency cycle. This technique is used for a master that mainly performs single
accesses or short bursts with idle cycles in between.