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125
SAM4CM Series [DATASHEET]
Atmel-11203C-ATARM-SAM4CM32-SAM4CM16-SAM4CM8-Datasheet_06-Oct-14
12.6.5.6MOV and MVN
Move and Move NOT.
Syntax
MOV{S}{
cond
}
Rd
,
Operand2
MOV{
cond
}
Rd
, #
imm16
MVN{S}{
cond
}
Rd
,
Operand2
where:
S
operation, see
“Conditional Execution”
.
is an optional suffix. If S is specified, the condition code flags are updated on the result
of
the
cond
is an optional condition code, see
“Conditional Execution”
.
Rd
is the destination register.
Operand2
is a flexible second operand. See
“Flexible Second Operand”
for details of the
options.
imm16
is any value in the range 0–65535.
Operation
The MOV instruction copies the value of
Operand2
into
Rd
.
When
Operand2
in a MOV instruction is a register with a shift other than LSL #0, the preferred syntax is the
corresponding shift instruction:
ASR{S}{cond} Rd, Rm, #n is the preferred syntax for MOV{S}{cond} Rd, Rm, ASR #n
LSL{S}{cond} Rd, Rm, #n is the preferred syntax for MOV{S}{cond} Rd, Rm, LSL #n if
n
!= 0
LSR{S}{cond} Rd, Rm, #n is the preferred syntax for MOV{S}{cond} Rd, Rm, LSR #n
ROR{S}{cond} Rd, Rm, #n is the preferred syntax for MOV{S}{cond} Rd, Rm, ROR #n
RRX{S}{cond} Rd, Rm is the preferred syntax for MOV{S}{cond} Rd, Rm, RRX.
Also, the MOV instruction permits additional forms of
Operand2
as synonyms for shift instructions:
MOV{S}{cond} Rd, Rm, ASR Rs is a synonym for ASR{S}{cond} Rd, Rm, Rs
MOV{S}{cond} Rd, Rm, LSL Rs is a synonym for LSL{S}{cond} Rd, Rm, Rs
MOV{S}{cond} Rd, Rm, LSR Rs is a synonym for LSR{S}{cond} Rd, Rm, Rs
MOV{S}{cond} Rd, Rm, ROR Rs is a synonym for ROR{S}{cond} Rd, Rm, Rs
See
“ASR, LSL, LSR, ROR, and RRX”
.
The MVN instruction takes the value of
Operand2
, performs a bitwise logical NOT operation on the value, and
places the result into
Rd
.
The MOVW instruction provides the same function as MOV, but is restricted to using the
imm16
operand.
Restrictions
SP and PC only can be used in the MOV instruction, with the following restrictions:
The second operand must be a register without shift
The S suffix must not be specified.
When
Rd
is PC in a MOV instruction:
Bit[0] of the value written to the PC is ignored
A branch occurs to the address created by forcing bit[0] of that value to 0.
Though it is possible to use MOV as a branch instruction, ARM strongly recommends the use of a BX or BLX
instruction to branch for software portability to the ARM instruction set.
Condition Flags