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SAM4CM Series [DATASHEET]
Atmel-11203C-ATARM-SAM4CM32-SAM4CM16-SAM4CM8-Datasheet_06-Oct-14
If LCDMODE is written to 3 while it is at 0, after the write resynchronization time (about 2 slow clock cycles),
the internal power supply source is selected and the embedded regulator is turned on, then after 15 slow
clock cycles, the SLCDC reset signal is released.
If LCDMODE is written to 0 while it is at 3, after the write resynchronization time (about 2 slow clock cycles),
the SLCDC reset signal, then after one slow clock cycle, the internal power supply source is deselected.
There are several restrictions concerning the write of the LCDMODE field:
The user must check that the previous power supply selection is done before writing LCDMODE again. To
do so, the user must check that the LCDS flag has the correct value. If LCDMODE is cleared, the LCDS flag
is cleared. If LCDMODE is set to 2 or 3, the LCDS flag is set.
Writing LCDMODE to 2 while it is at 3 or writing LCDMODE to 3 while it is at 2 is forbidden and has no effect.
Before writing LCDMODE to 2, the user must ensure that the external power supply is ready and supplies
the VDDLCD pin.
Before writing LCDMODE to 3, the user must ensure that the external power supply does not supply the
VDDLCD pin.
The SLCD can be used in all low-power modes.
20.4.5 Using Backup Battery/Automatic Power Switch
The power switch automatically selects either VDDBU or VDDIO as a power source.
As soon as VDDIO is present (higher than 1.9V), it supplies the backup area of the device (VDDBU_SW = VDDIO)
even if the voltage of VDDBU is higher than VDDIO. If not, the backup area is supplied by the VDDBU voltage
source (VDDBU_SW = VDDBU). For more information on power supply schematics, refer to the section “Power
Supply”.
20.4.6 Supply Monitor
The SUPC embeds a supply monitor located in the VDDBU_SW power domain and which monitors VDDIO power
supply.
The supply monitor can be used to prevent the processor from falling into an unpredictable state if the main power
supply drops below a certain level.
The threshold of the supply monitor is programmable. It can be selected from 1.9V to 3.4V by steps of 100 mV.
This threshold is configured in the SMTH field of the Supply Controller Supply Monitor Mode register
(SUPC_SMMR).
The supply monitor can also be enabled during one slow clock period on every one of either 32, 256 or 2048 slow
clock periods, depending on the user selection. This is configured in the SMSMPL field in SUPC_SMMR.
Enabling the supply monitor for such reduced times divides the typical supply monitor power consumption by
factors of 2, 16 or 128, respectively, if continuous monitoring of the VDDIO power supply is not required.
A supply monitor detection can either generate a system reset (vddcore_nreset signal is asserted) or a system
wake-up. Generating a system reset when a supply monitor detection occurs is enabled by setting the SMRSTEN
bit in SUPC_SMMR.
Waking up the system when a supply monitor detection occurs is enabled by setting the SMEN bit in the Supply
Controller Wake-up Mode register (SUPC_WUMR).
The SUPC provides two status bits for the supply monitor in the SUPC_SR. These bits determines whether the
last wake-up was due to the supply monitor:
the SMOS bit provides real-time information, updated at each measurement cycle or updated at each Slow
Clock cycle, if the measurement is continuous.
the SMS bit provides saved information and shows a supply monitor detection has occurred since the last
read of SUPC_SR.