參數(shù)資料
型號: R5F212ACSDFP
元件分類: 微控制器/微處理器
英文描述: 16-BIT, FLASH, 20 MHz, RISC MICROCONTROLLER, PQFP48
封裝: 10 X 10 MM, 0.50 MM PITCH, PLASTIC, LQFP-48
文件頁數(shù): 40/138頁
文件大?。?/td> 492K
代理商: R5F212ACSDFP
221
4317K–AVR–03/2013
AT90PWM2/3/2B/3B
All the receiver error flags are valid only when the RxC bit is set and until the UDR register is
read.
19.5.5.1
Parity Checker
The parity checker of the EUSART is available only when data bits are level encoded and
behaves as is USART mode (See Parity checker of the USART).
19.5.5.2
OverRun
The Data OverRun (DOR bit of USCRA) flag indicates data loss due to a receiver buffer full con-
dition. This flag operates as in USART mode (See USART section).
19.6
EUSART Registers Description
19.6.1
USART I/O Data Register – UDR
Bit 7:0 – RxB7:0: Receive Data Buffer (read access)
Bit 7:0 – TxB7:0: Transmit Data Buffer (write access)
This register is common to the USART and EUSART interfaces for Transmit Data Buffer Regis-
ter and Receive Data Buffer Register. See description for UDR register in USART.
19.6.2
EUSART I/O Data Register – EUDR
Bit 7:0 – RxB15:8: Receive Data Buffer (read access)
Bit 7:0 – TxB15:8: Transmit Data Buffer (write access)
This register provide an extension to the UDR register when EUSART is used with more than 8
bits.
19.6.2.1
UDR/EUDR data access with character size up to 8 bits
When the EUSART is used with 8 or less bits, only the UDR register is used for dta access.
19.6.2.2
UDR/EUDR data access with 9 bits per character
When the EUSART is used with 9 bits character, the behavior is different of the standart USART
mode, the UDR register is used in combinaison with the first bit of EUDR (EUDR:0) for data
access, the RxB8/TxB8 bit is not used.
Bit
765
43
21
0
RXB[7:0]
UDR (Read)
TXB[7:0]
UDR (Write)
Read/Write
R/W
Initial Value
000
00
0
Bit
765
43
21
0
RXB[15:8]
EUDR (Read)
TXB[15:8]
EUDR (Write)
Read/Write
R/W
Initial Value
000
00
10
0
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