參數(shù)資料
型號： R5F212ACSDFP
元件分類： 微控制器/微處理器
英文描述： 16-BIT, FLASH, 20 MHz, RISC MICROCONTROLLER, PQFP48
封裝： 10 X 10 MM, 0.50 MM PITCH, PLASTIC, LQFP-48
文件頁數(shù)： 31/138頁
文件大?。?/td> 492K
代理商： R5F212ACSDFP
213
4317K–AVR–03/2013
AT90PWM2/3/2B/3B
The EUSART supports more serial frame formats than the standard USART interface:
Asynchonous frames
–
Standard bit level encoded
–
Manchester bit encoded
Synchronous frames
–
In this mode only the Standard bit level encoded is available
19.3
Serial Frames
A serial frame is defined to be one character of data bits with synchronization bits (start and stop
bits), and optionally a parity bit for error checking.
19.3.1
Frame Formats
The EUSART allows to receive and transmit serial frame with the following format:
1 start bit
5, 6, 7, 8, 9, 13, 14,15,16,17 data bits
data bits and start bit level encoded or Manchester encoded
data transmition MSB or LSB first (bit ordering)
no, even or odd parity bit
1 or 2 stop bits:
–
Stop bits insertion for transmition
–
Stop bits value read access in reception
The frame format used by the EUSART can be configured th rough the fo llowing
USART/EUSART registers:
UTxS3:0 and URxS3:0 (EUCSRA of EUSART register) select the number of data bits per
frame
UPM1:0 bits enable and set the type of parity bit (when configured in Manchester mode, the
parity should be fixed to none).
USBS (UCSRC register of USART) and EUSBS (EUCSRB register of EUSART) select the num-
ber of stop bits to be processed respectively by the transmiter and the receiver. The receiver
stores the two stop bit values when configured in Manchester mode. When configured in level
encoded mode, the second stop bit is ignored (behavior similar as the USART).
19.3.2
Parity Bit Calculation
The parity bit behavior is similar to the USART mode, except for the Manchester encoded mode,
where no parity bit can be inserted or detected (should be configured to none with the
UPM1:0
bits. The parity bit is calculated by doing an exclusive-or of all the data bits. If odd parity is used,
the result of the exclusive or is inverted. The relation between the parity bit and data bits is as
follows:
P
even
Parity bit using even parity
P
odd
Parity bit using odd parity
d
n
Data bit n of the character
If used, the parity bit is located between the last data bit and first stop bit of a serial frame.
P
even
d
n
1
–
d
3
d
2
d
1
d
0
P
odd
d
n
1
–
d
3
d
2
d
1
d
0
1
=
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
R5F212ACSDFP#U0 制造商:Renesas Electronics Corporation 功能描述:IC MCU 16BIT R8C2A 64LQFP
R5F212ACSDFP#V2 制造商:Renesas Electronics Corporation 功能描述:R8C/2A 128+0/7.5 64LQFP 10X10 -40 TO +85 - Trays 制造商:Renesas Electronics Corporation 功能描述:IC MCU 16BIT 128KB FLASH 64LQFP
R5F212ACSDXXXFA 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:RENESAS MCU R8C FAMILY / R8C/2x SERIES
R5F212ACSDXXXFP 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:RENESAS MCU R8C FAMILY / R8C/2x SERIES
R5F212ACSNFA 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:MCU
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