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參數(shù)資料
| 型號： | R5F21274JFP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 16-BIT, FLASH, 20 MHz, MICROCONTROLLER, PQFP32 |
| 封裝： | 7 X 7 MM, 0.80 MM PITCH, PLASTIC, LQFP-32 |
| 文件頁數(shù)： | 41/52頁 |
| 文件大小： | 620K |
| 代理商： | R5F21274JFP |
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63
ATmega165A/PA/325A/PA/3250A/PA/645A/P/6450A/P [DATASHEET]
8285E–AVR–02/2013
Switching between input with pull-up and output low generates the same problem. The user must use either the tri-
state ({DDxn, PORTxn} = 0b00) or the output high state ({DDxn, PORTxn} = 0b11) as an intermediate step.
Table 14-1 on page 63 summarizes the control signals for the pin value.
14.2.4
Reading the pin value
Independent of the setting of Data Direction bit DDxn, the port pin can be read through the PINxn Register bit. As
shown in Figure 14-2, the PINxn Register bit and the preceding latch constitute a synchronizer. This is needed to
avoid metastability if the physical pin changes value near the edge of the internal clock, but it also introduces a
delay. Figure 14-3 shows a timing diagram of the synchronization when reading an externally applied pin value.
The maximum and minimum propagation delays are denoted t
pd,max and tpd,min respectively.
Figure 14-3. Synchronization when reading an externally applied pin value.
Consider the clock period starting shortly after the first falling edge of the system clock. The latch is closed when
the clock is low, and goes transparent when the clock is high, as indicated by the shaded region of the “SYNC
LATCH” signal. The signal value is latched when the system clock goes low. It is clocked into the PINxn Register at
the succeeding positive clock edge. As indicated by the two arrows tpd,max and tpd,min, a single signal transition
on the pin will be delayed between and 1 system clock period depending upon the time of assertion.
When reading back a software assigned pin value, a nop instruction must be inserted as indicated in Figure 14-4
on page 64. The out instruction sets the “SYNC LATCH” signal at the positive edge of the clock. In this case, the
delay tpd through the synchronizer is one system clock period.
Table 14-1.
Port pin configurations.
DDxn
PORTxn
PUD
(in MCUCR)
I/O
Pull-up
Comment
0
X
Input
No
Tri-state (Hi-Z)
0
1
0
Input
Yes
Pxn will source current if ext. pulled low.
0
1
Input
No
Tri-state (Hi-Z)
1
0
X
Output
No
Output Low (Sink)
1
X
Output
No
Output High (Source)
XXX
in r17, PINx
0x00
0xFF
INSTRUCTIONS
SYNC LATCH
PINxn
r17
XXX
SYSTEM CLK
t
pd, max
t pd, min
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| R5F21274JFP#U0 | 功能描述:MCU FLASH 2K FLASH 16K 32LQFP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - 微控制器， 系列:R8C/2x/27 標(biāo)準(zhǔn)包裝:250 系列:80C 核心處理器:8051 芯體尺寸:8-位 速度:16MHz 連通性:EBI/EMI，I²C，UART/USART 外圍設(shè)備:POR，PWM，WDT 輸入/輸出數(shù):40 程序存儲器容量:- 程序存儲器類型:ROMless EEPROM 大小:- RAM 容量:256 x 8 電壓 - 電源 (Vcc/Vdd):4.5 V ~ 5.5 V 數(shù)據(jù)轉(zhuǎn)換器:A/D 8x10b 振蕩器型:內(nèi)部 工作溫度:-40°C ~ 85°C 封裝/外殼:68-LCC（J 形引線） 包裝:帶卷 (TR) |
| R5F21274JFP#W4 | 制造商:Renesas Electronics Corporation 功能描述:MCU 3/5V - Tape and Reel |
| R5F21274JXXXFP | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:SINGLE-CHIP 16-BIT CMOS MCU |
| R5F21274KFP | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:RENESAS 16-BIT SINGLE-CHIP MCU R8C FAMILY / R8C/2x SERIES |
| R5F21274KXXXFP | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:SINGLE-CHIP 16-BIT CMOS MCU |
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