參數(shù)資料
型號(hào)： R5F21274JFP
元件分類(lèi)： 微控制器/微處理器
英文描述： 16-BIT, FLASH, 20 MHz, MICROCONTROLLER, PQFP32
封裝： 7 X 7 MM, 0.80 MM PITCH, PLASTIC, LQFP-32
文件頁(yè)數(shù)： 16/52頁(yè)
文件大?。?/td> 620K
代理商： R5F21274JFP
40
ATmega165A/PA/325A/PA/3250A/PA/645A/P/6450A/P [DATASHEET]
8285E–AVR–02/2013
disabled and it will not be consuming power. When turned on again, the user must allow the reference to start up
before the output is used. If the reference is kept on in sleep mode, the output can be used immediately. Refer to
”Internal voltage reference” on page 46 for details on the start-up time.
10.10.5
Watchdog Timer
If the Watchdog Timer is not needed in the application, the module should be turned off. If the Watchdog Timer is
enabled, it will be enabled in all sleep modes, and hence, always consume power. In the deeper sleep modes, this
will contribute significantly to the total current consumption. Refer to ”Watchdog Timer” on page 47 for details on
how to configure the Watchdog Timer.
10.10.6
Port pins
When entering a sleep mode, all port pins should be configured to use minimum power. The most important is then
to ensure that no pins drive resistive loads. In sleep modes where both the I/O clock (clk
I/O) and the ADC clock
(clk
ADC) are stopped, the input buffers of the device will be disabled. This ensures that no power is consumed by
the input logic when not needed. In some cases, the input logic is needed for detecting wake-up conditions, and it
will then be enabled. Refer to the section ”Digital Input Enable and Sleep modes” on page 65 for details on which
pins are enabled. If the input buffer is enabled and the input signal is left floating or have an analog signal level
close to V
CC/2, the input buffer will use excessive power.
For analog input pins, the digital input buffer should be disabled at all times. An analog signal level close to V
CC/2
on an input pin can cause significant current even in active mode. Digital input buffers can be disabled by writing to
the Digital Input Disable Registers (DIDR1 and DIDR0). Refer to ”DIDR1 – Digital Input Disable Register 1” on
10.10.7
JTAG Interface and On-chip Debug System
If the On-chip debug system is enabled by the OCDEN Fuse and the chip enter Power down or Power save sleep
mode, the main clock source remains enabled. In these sleep modes, this will contribute significantly to the total
current consumption. There are three alternative ways to avoid this:
Disable OCDEN Fuse
Disable JTAGEN Fuse
Write one to the JTD bit in MCUCR
The TDO pin is left floating when the JTAG interface is enabled while the JTAG TAP controller is not shifting data.
If the hardware connected to the TDO pin does not pull up the logic level, power consumption will increase. Note
that the TDI pin for the next device in the scan chain contains a pull-up that avoids this problem. Writing the JTD bit
in the MCUCR register to one or leaving the JTAG fuse unprogrammed disables the JTAG interface.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
R5F21274JFP#U0 功能描述:MCU FLASH 2K FLASH 16K 32LQFP RoHS:否 類(lèi)別:集成電路 (IC) >> 嵌入式 - 微控制器， 系列:R8C/2x/27 標(biāo)準(zhǔn)包裝:250 系列:80C 核心處理器:8051 芯體尺寸:8-位 速度:16MHz 連通性:EBI/EMI，I²C，UART/USART 外圍設(shè)備:POR，PWM，WDT 輸入/輸出數(shù):40 程序存儲(chǔ)器容量:- 程序存儲(chǔ)器類(lèi)型:ROMless EEPROM 大小:- RAM 容量:256 x 8 電壓 - 電源 (Vcc/Vdd):4.5 V ~ 5.5 V 數(shù)據(jù)轉(zhuǎn)換器:A/D 8x10b 振蕩器型:內(nèi)部 工作溫度:-40°C ~ 85°C 封裝/外殼:68-LCC（J 形引線） 包裝:帶卷 (TR)
R5F21274JFP#W4 制造商:Renesas Electronics Corporation 功能描述:MCU 3/5V - Tape and Reel
R5F21274JXXXFP 制造商:RENESAS 制造商全稱(chēng):Renesas Technology Corp 功能描述:SINGLE-CHIP 16-BIT CMOS MCU
R5F21274KFP 制造商:RENESAS 制造商全稱(chēng):Renesas Technology Corp 功能描述:RENESAS 16-BIT SINGLE-CHIP MCU R8C FAMILY / R8C/2x SERIES
R5F21274KXXXFP 制造商:RENESAS 制造商全稱(chēng):Renesas Technology Corp 功能描述:SINGLE-CHIP 16-BIT CMOS MCU
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