參數(shù)資料
型號(hào): R5F21274JFP
元件分類: 微控制器/微處理器
英文描述: 16-BIT, FLASH, 20 MHz, MICROCONTROLLER, PQFP32
封裝: 7 X 7 MM, 0.80 MM PITCH, PLASTIC, LQFP-32
文件頁(yè)數(shù): 27/52頁(yè)
文件大?。?/td> 620K
代理商: R5F21274JFP
50
ATmega165A/PA/325A/PA/3250A/PA/645A/P/6450A/P [DATASHEET]
8285E–AVR–02/2013
1.
In the same operation, write a logic one to WDCE and WDE. A logic one must be written to WDE even
though it is set to one before the disable operation starts.
2.
Within the next four clock cycles, write a logic 0 to WDE. This disables the Watchdog.
In safety level 2, it is not possible to disable the Watchdog Timer, even with the algorithm described above. See
Bits 2:0 – WDP2, WDP1, WDP0: Watchdog Timer Prescaler 2, 1, and 0
The WDP2, WDP1, and WDP0 bits determine the Watchdog Timer prescaling when the Watchdog Timer is
enabled. The different prescaling values and their corresponding Timeout Periods are shown in Table 11-2.
Note:
The following code example shows one assembly and one C function for turning off the WDT. The example
assumes that interrupts are controlled (for example, by disabling interrupts globally) so that no interrupts will occur
during execution of these functions.
Table 11-2.
Watchdog Timer Prescale Select
WDP2
WDP1
WDP0
Number of WDT
oscillator cycles
Typical time-out at
V
CC = 3.0V
Typical time-out at
V
CC = 5.0V
0
16K cycles
15.4ms
14.7ms
0
1
32K cycles
30.8ms
29.3ms
0
1
0
64K cycles
61.6ms
58.7ms
0
1
128K cycles
0.12s
1
0
256K cycles
0.25s
0.23s
1
0
1
512K cycles
0.49s
0.47s
1
0
1,024K cycles
1.0s
0.9s
1
2,048K cycles
2.0s
1.9s
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