參數(shù)資料
型號: R5F21274JFP
元件分類: 微控制器/微處理器
英文描述: 16-BIT, FLASH, 20 MHz, MICROCONTROLLER, PQFP32
封裝: 7 X 7 MM, 0.80 MM PITCH, PLASTIC, LQFP-32
文件頁數(shù): 18/52頁
文件大?。?/td> 620K
代理商: R5F21274JFP
42
ATmega165A/PA/325A/PA/3250A/PA/645A/P/6450A/P [DATASHEET]
8285E–AVR–02/2013
Bit 5 – BODSE: BOD Sleep Enable
BODSE enables setting of BODS control bit, as explained in BODS bit description. BOD disable is controlled by a
timed sequence.
10.11.3
PRR – Power Reduction Register
Bit 7:4 - Reserved
These bits are reserved and will always read as zero.
Bit 3 - PRTIM1: Power Reduction Timer/Counter1
Writing a logic one to this bit shuts down the Timer/Counter1 module. When the Timer/Counter1 is enabled, opera-
tion will continue like before the shutdown.
Bit 2 - PRSPI: Power Reduction Serial Peripheral Interface
Writing a logic one to this bit shuts down the Serial Peripheral Interface by stopping the clock to the module. When
waking up the SPI again, the SPI should be re initialized to ensure proper operation.
Bit 1 - PRUSART0: Power Reduction USART0
Writing a logic one to this bit shuts down the USART by stopping the clock to the module. When waking up the
USART again, the USART should be re initialized to ensure proper operation.
Bit 0 - PRADC: Power Reduction ADC
Writing a logic one to this bit shuts down the ADC. The ADC must be disabled before shut down. The analog com-
parator cannot use the ADC input MUX when the ADC is shut down.
Note:
The Analog Comparator is disabled using the ACD-bit in the ”ACSR – Analog Comparator Control and Status Register”
Bit
7
6
5
4
3
2
1
0
(0x64)
PRTIM1
PRSPI
PRUSART0
PRADC
PRR
Read/Write
R
R/W
Initial Value
0
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相關代理商/技術參數(shù)
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