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參數(shù)資料
| 型號： | QL6325-4PB516C |
| 廠商： | QUICKLOGIC CORP |
| 元件分類： | FPGA |
| 英文描述： | FPGA, 1536 CLBS, 320640 GATES, PBGA516 |
| 封裝： | 1.27 MM PITCH, PLASTIC, BGA-516 |
| 文件頁數(shù)： | 9/38頁 |
| 文件大?。?/td> | 1093K |
| 代理商： | QL6325-4PB516C |
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2002 QuickLogic Corporation
17
QL6325 Eclipse Data Sheet Rev C
Power vs. Operating Frequency
The basic power equation which best models power consumption is given below:
P
TOTAL
= 0.350 +
f[0.0031
η
LC +
0.0948
η
CKBF +
0.01
η
CLBF+
0.0263
η
CKLD+
0.543
η
RAM
+ 0.20
η
PLL+
0.0035
η
INP +
0.0257
η
OUTP]
(mW)
Where
η
LC is the total number of logic cells in the design
η
CKBF = # of clock buffers
η
CLBF = # of column clock buffers
η
CKLD = # of loads connected to the column clock buffers
η
RAM = # of RAM blocks
η
PLL = # of PLLs
η
INP is the number of input pins
η
OUTP is the number of output pins
exhibits the power consumption in an Eclipse QL6325 device. The chip was filled
with (300) 8-bit counters
approximately 76% logic cell utilization.
Figure 20: Power Consumption
illustrates the theoretical worst-case scenarios for 50%, 70%, and 90% utilizations
of the 6600-516 package. The resources of the device are divided exactly in half; meaning,
for 50% utilization, exactly 50% of the I/Os, Logic Cells, RAM blocks, clock network, etc
are utilized. These situations may never occur in a real design, but they do provide a very
rough quantitative measure of power consumption when talking in terms of 50% or 70%
utilization of an Eclipse device.
Power vs Freq. (Counter_300)
0
0.5
1
1.5
2
2.5
0
20
40
60
80
100
120
140
Frequency (Mhz)
Po
w
er
(W
)
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