參數(shù)資料
型號: QL6325-4PB516C
廠商: QUICKLOGIC CORP
元件分類: FPGA
英文描述: FPGA, 1536 CLBS, 320640 GATES, PBGA516
封裝: 1.27 MM PITCH, PLASTIC, BGA-516
文件頁數(shù): 37/38頁
文件大?。?/td> 1093K
代理商: QL6325-4PB516C
8
2002 QuickLogic Corporation
QL6325 Eclipse Data Sheet Rev C
Figure 12: Eclipse Input Register Cell
Table 6: Input Register Cell
Symbol
Parameter
Value (ns)
Input Register Cell Only
Min
Max
t
ISU
Input register setup time: time the synchronous input of the flip-flop must be stable
before the active clock edge
3.12
-
t
IHL
Input register hold time: time the synchronous input of the flip-flop must be stable
after the active clock edge
0
-
t
ICO
Input register clock to out: time taken by the flip-flop to output after the active clock
edge
-
1.08
t
IRST
Input register reset delay: time between when the flip-flop is “reset”(low) and when
the output is consequently “reset” (low)
-
0.99
t
IESU
Input register clock enable setup time: time “enable” must be stable before the
active clock edge
0.37
-
t
IEH
Input register clock enable hold time: time “enable” must be stable after the active
clock edge
0
-
PAD
tIN, tINI
tICLK
tISU
tSID
+
-
Q E
D
R
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