參數(shù)資料
型號: QL6325-4PB516C
廠商: QUICKLOGIC CORP
元件分類: FPGA
英文描述: FPGA, 1536 CLBS, 320640 GATES, PBGA516
封裝: 1.27 MM PITCH, PLASTIC, BGA-516
文件頁數(shù): 34/38頁
文件大?。?/td> 1093K
代理商: QL6325-4PB516C
2002 QuickLogic Corporation
5
QL6325 Eclipse Data Sheet Rev C
Figure 8: RAM Module
Table 4: RAM Cell Synchronous Write Timing
Symbol
Parameter
Value (ns)
RAM Cell Synchronous Write Timing
Min
Max
t
SWA
WA setup time to WCLK: time the WRITE ADDRESS must be stable before the
active edge of the WRITE CLOCK
0.675
-
t
HWA
WA hold time to WCLK: time the WRITE ADDRESS must be stable after the active
edge of the WRITE CLOCK
0
-
t
SWD
WD setup time to WCLK: time the WRITE DATA must be stable before the active
edge of the WRITE CLOCK
0.654
-
t
HWD
WD hold time to WCLK: time the WRITE DATA must be stable after the active edge
of the WRITE CLOCK
0
-
t
SWE
WE setup time to WCLK: time the WRITE ENABLE must be stable before the active
edge of the WRITE CLOCK
0.623
-
t
HWE
WE hold time to WCLK: time the WRITE ENABLE must be stable after the active
edge of the WRITE CLOCK
0
-
tWCRD
WCLK to RD (WA = RA): time between the active WRITE CLOCK edge and the
time when the data is available at RD
-
4.38
WA
WD
WE
WCLK
RE
RCLK
RA
RD
RAM Module
[9:0]
[17:0]
[9:0]
[17:0]
ASYNCRD
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