參數(shù)資料
型號(hào)： QL6325-4PB516C
廠商： QUICKLOGIC CORP
元件分類： FPGA
英文描述： FPGA, 1536 CLBS, 320640 GATES, PBGA516
封裝： 1.27 MM PITCH, PLASTIC, BGA-516
文件頁數(shù)： 35/38頁
文件大?。?/td> 1093K
代理商： QL6325-4PB516C
6
2002 QuickLogic Corporation
QL6325 Eclipse Data Sheet Rev C
Figure 9: RAM Cell Synchronous Write Timing
Table 5: RAM Cell Synchronous & Asynchronous Read Timing
Symbol
Parameter
Value (ns)
RAM Cell Synchronous Read Timing
Min
Max
t
SRA
RA setup time to RCLK: time the READ ADDRESS must be stable before the active
edge of the READ CLOCK
0.686
-
tHRA
RA hold time to RCLK: time the READ ADDRESS must be stable after the active
edge of the READ CLOCK
0
-
t
SRE
RE setup time to WCLK: time the READ ENABLE must be stable before the active
edge of the READ CLOCK
0.243
-
t
HRE
RE hold time to WCLK: time the READ ENABLE must be stable after the active
edge of the READ CLOCK
0
-
tRCRD
RCLK to RD: time between the active READ CLOCK edge and the time when the
data is available at RD
-
4.38
RAM Cell Asynchronous Read Timing
rPDRD
RA to RD: time between when the READ ADDRESS is input and when the DATA
is output
-
2.06
tSWA
tSWD
tSWE
tHWA
tHWD
tHWE
tWCRD
old data
new data
WCLK
WA
WD
WE
RD
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