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參數(shù)資料
| 型號(hào)： | QL6325-4PB516C |
| 廠商： | QUICKLOGIC CORP |
| 元件分類： | FPGA |
| 英文描述： | FPGA, 1536 CLBS, 320640 GATES, PBGA516 |
| 封裝： | 1.27 MM PITCH, PLASTIC, BGA-516 |
| 文件頁數(shù)： | 13/38頁 |
| 文件大?。?/td> | 1093K |
| 代理商： | QL6325-4PB516C |
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20
2002 QuickLogic Corporation
QL6325 Eclipse Data Sheet Rev C
JTAG
Figure 24: JTAG Block Diagram
Microprocessors and Application Specific Integrated Circuits (ASICs) pose many design
challenges, not in the least of which concerns the accessibility of test points. The Joint Test
Access Group (JTAG) formed in response to this challenge, resulting in IEEE standard
1149.1, the Standard Test Access Port and Boundary Scan Architecture.
The JTAG boundary scan test methodology allows complete observation and control of the
boundary pins of a JTAG-compatible device through JTAG software. A Test Access Port
(TAP) controller works in concert with the Instruction Register (IR), which allow users to run
three required tests along with several user-defined tests.
JTAG tests allow users to reduce system debug time, reuse test platforms and tools, and reuse
subsystem tests for fuller verification of higher level system elements.
TCK
TMS
TRSTB
RDI
TDO
Instruction Decode
&
Control Logic
TAp Controller
State Machine
(16 States)
Instruction Register
Boundary-Scan Register
(Data Register)
Mux
Bypass
Register
Mux
Internal
Register
I/O Registers
User Defined Data Register
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