參數(shù)資料
型號(hào)： QL6325-4PB516C
廠商： QUICKLOGIC CORP
元件分類： FPGA
英文描述： FPGA, 1536 CLBS, 320640 GATES, PBGA516
封裝： 1.27 MM PITCH, PLASTIC, BGA-516
文件頁(yè)數(shù)： 16/38頁(yè)
文件大小： 1093K
代理商： QL6325-4PB516C
2002 QuickLogic Corporation
23
QL6325 Eclipse Data Sheet Rev C
Table 17: Dedicated Pin Descriptions
Pin
Function
Description
CLK
High-drive input and/or global
clock network driver
Can be configured as either input or global clock
I/O(A)
Input/Output pin
The I/O pin is a bi-directional pin, configurable to either an input-
only, output-only, or bi-directional pin. The A inside the
parenthesis means that the I/O is located in Bank A. If an I/O is
not used, SpDE (QuickWorks Tool) provides the option of tying
that pin to GND, V
CC, or TriState during programming.
V
CC
Power supply pin
Connect to 2.5 V supply
V
CCIO(A)
Input voltage tolerance pin
This pin provides the flexibility to interface the device with either a
3.3 V device or a 2.5 V device. The A inside the parenthesis
means that V
CCIO is located in BANK A. Every I/O pin in Bank A
will be tolerant of VCCIO input signals and will output VCCIO level
signals. This pin must be connected to either 3.3 V or V
CC.
GND
Ground pin
Connect to ground
PLLIN
PLL clock input
Clock input for PLL
DEDCLK
Dedicated clock pin
Low skew global clock
GNDPLL
Ground pin for PLL
Connect to GND
INREF(A)
Differential reference voltage
The INREF is the reference voltage pin for GTL+, SSTL2, and
STTL3 standards. Follow the recommendations provided in
Table 14 for the appropriate standard. The A inside the
parenthesis means that INREF is located in BANK A. This pin
should be tied to GND if not needed.
PLLOUT
PLL output pin
Dedicated PLL output pin; otherwise, may be left unconnected
IOCTRL(A)
Highdrive input
This pin provides fast RESET, SET, CLOCK, and ENABLE access
to the I/O cell flip-flops, providing fast clock-to-out and fast I/O
response times. This pin can also double as a high-drive pin to the
internal logic cells. The A inside the parenthesis means that
IOCTRL is located in Bank A. This pin should be tied to GND or
V
CC if it is not used.
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