參數(shù)資料
型號(hào): PXASCC
廠商: NXP Semiconductors N.V.
英文描述: CMOS 16-bit communications microcontroller(CMOS 16位通信微控制器)
中文描述: 的CMOS 16位微控制器通信的CMOS(16位通信微控制器)
文件頁(yè)數(shù): 37/42頁(yè)
文件大?。?/td> 229K
代理商: PXASCC
Philips Semiconductors
Preliminary specification
XA-SCC
CMOS 16-bit communications microcontroller
1999 Mar 29
37
CLKOUT
A
RAS
CASL
(CASH STAYS HIGH)
OE
D[7:0]
t
CHAV
t
CHSL
SU01140
t
CHAV
t
CHSL
t
CHAV
t
CHAV
RAS ADDRESS
CAS ADDRESS EVEN
CAS ADDRESS ODD
LS BYTE
MS BYTE
t
DIH
(NOTE 2)
NOTE 2
t
CHSL
t
CHSH
t
CHSH
t
CHAH
t
CHAH
t
CHAH
t
DIS
t
DIS
t
AVSL
t
CPWH
t
AVSL
Figure 19. 16 Bit Read on 8 Bit Bus, DRAM (both FPM and EDO)
ClkOut
A
RAS
CASL
OE
SU01141
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
4 Byte Fetch is shown on 8 bit bus, burst can be 2 to 16 bytes.
Data bus is sampled on the rising edge of clock 6, and every three clocks thereafter (clocks 6, 9, 12, and 15 in this example).
NOTE 2: If data is held valid on the bus until the earliest of CAS, RAS, or OE rises, then the hold time is met.
t
CHAV
D7–D0
t
DIS
LS BYTE
MS BYTE
LS BYTE
MS BYTE
t
DIH
(NOTE 2)
t
DIH
(NOTE 2)
t
CPWH
t
CHSH
t
CHSL
t
AVSL
t
AVSL
t
CHSL
t
CHAH
t
CHSH
t
CHSH
t
OHDE
RAS ADDR
CAS ADDR
(EVEN)
CAS ADDR
(ODD)
CAS ADDR
(EVEN)
CAS ADDR
(ODD)
Figure 20. DRAM FPM (Fast Page Mode) Burst Code Fetch on 8 Bit Bus
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