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參數(shù)資料
| 型號： | PXASCC |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | CMOS 16-bit communications microcontroller(CMOS 16位通信微控制器) |
| 中文描述： | 的CMOS 16位微控制器通信的CMOS（16位通信微控制器） |
| 文件頁數(shù)： | 23/42頁 |
| 文件大?。?/td> | 229K |
| 代理商： | PXASCC |
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Philips Semiconductors
Preliminary specification
XA-SCC
CMOS 16-bit communications microcontroller
1999 Mar 29
23
DMA Registers
In addition to the 16-bit Global DMA Interrupt Register (which is
shared by all eight DMA channels), each DMA channel has seven
control registers and a four-byte Data FIFO. The four Rx DMA
channels have one additional register, the Rx Character Time Out
Register. All DMA registers can be read and written in Memory
Mapped Register (MMR) space. These registers are summarized
below.
Global DMA Interrupt Register (not shown in figure): All DMA
interrupt flags are in this register .
DMA Control Register: Contains the master mode select and
interrupt enable bits for the channel.
Segment Register: Holds A23–A16 (the current segment) of the
24-bit data buffer address.
Buffer Base Register: Holds a pointer (A15–A8) to the lowest byte
in the memory buffer.
Buffer Bound Register: Points to the first out-of-bounds address
above a circular buffer.
Address Pointer Register: Points to a single byte or word in the
data buffer in memory. The 24-bit DMA address is formed by
concatenating the contents of the Segment Register [A23–A16]
with the contents of the Address Pointer Register [A15–A0].
Byte Count Register: Holds the initial number of bytes to be
transferred. In Tx Chaining mode, this register is not used
because the byte count is brought into the byte counter from
buffer headers in memory.
FIFO Control & Status Register: Holds the queuing order and
full/empty status for the Data FIFO Registers.
Data FIFO Registers: A four-byte data FIFO buffer internal to the
DMA channel.
Rx Char Time Out Register (RxCTOR, Rx DMA channels only):
Holds the initial value for an 8-bit character timeout countdown
timer which can generate an interrupt.
Quad Serial Communications Controllers with
Autobaud
Asynchronous features:
–
Asynchronous transfers up to 921.6Kbps
–
Can monitor input stream for up to four match characters per
receiver
–
5, 6, 7, or 8 data bits per character.
–
1, 1.5, or 2 Stop bits per character.
–
Even or Odd parity generate and check.
–
Parity, Rx Overrun, and Framing Error detection.
–
Break detection.
–
Supports hardware Autobaud detection and response up to
921.6Kbps.
SDLC/HDLC features:
–
Automatic Flag and Abort Character generation and
recognition.
–
Automatic CRC generation and checking (can be disabled for
“pass-thru.”)
–
Automatic zero-bit insertion and stripping.
–
Automatic partial byte residue code generation.
–
14-bit Packet byte count stored in memory with received packet
by DMA.
Synchronous character oriented protocol features:
–
Automatic CRC generation and checking.
–
One (Monosync) or two (Bisync) sync characters option.
–
External Sync option.
Transparent mode for bit-streaming applications.
Data encoding/decoding options:
–
FM0 (Biphase Space)
–
FM1 (Biphase Mark)
–
NRZ
–
NRZI
Programmable Baud Rate Generator, and 7/8 Clock Prescaler
option.
Auto Echo and Local Loopback modes.
Supports hardware V.54/2047 generation and checking.
IDL (2B + D) supported on three SCC channels. Supports both “8
bit” and “10 bit” IDL.
IDL Time Division Multiplexor
SCC0, SCC1, and SCC2 can be internally connected to the on-chip
IDL Interface, a glueless industry standard interface to Layer One
devices such as U-Chips or S/T chips. Thus connected, the three
SCCs can efficiently support the ISDN B1, B2, and D channels,
while the IDL Interface time-multiplexes and demultiplexes the
outgoing and incoming serial data streams.
If software enables the IDL interface, then SCC0 is connected to
IDL. Optionally, the software can also connect SCC1 and SCC2 to
the IDL interface. SCC3 cannot be connected to the IDL interface.
See the IDL chapter in the XA-SCC User Manual.
In Figure 7, SCC0 is connected to IDL because IDL has been
enabled by software. Software, in this example has also connected
SCC1 to IDL, and has bypassed IDL for SCC2. SCC3 cannot be
connected to IDL. If there are pins not being used by any of the
SCCs, software can assign alternate functions to those pins; see the
pin steering logic in the “Pins” appendix of the XA-SCC User
Manual. For complete documentation on the IDL interface, see the
IDL chapter in the XA-SCC User Manual.
SCP Serial Interface Controller
The SCP Interface provides a full duplex, industry standard
synchronous serial communication bus, similar to SPI and
Microwire. SCP can be used to transfer control and status
information to other chips, and for accessing serial flash devices.
See the IDL interface chapter in the XA-SCC User Manual.
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