參數(shù)資料
型號(hào)： PXASCC
廠商： NXP Semiconductors N.V.
英文描述： CMOS 16-bit communications microcontroller(CMOS 16位通信微控制器)
中文描述： 的CMOS 16位微控制器通信的CMOS（16位通信微控制器）
文件頁數(shù)： 19/42頁
文件大?。?/td> 229K
代理商： PXASCC
Philips Semiconductors
Preliminary specification
XA-SCC
CMOS 16-bit communications microcontroller
1999 Mar 29
19
Bus Interface Pins
For this discussion, see Figure 4.
SU01125
CS5, RAS5, (or P3.1, RTS1)
CS4, RAS4, (or P3.0, RTClk1)
CS3, RAS3
CS2, RAS2
CS1, RAS1
CS0
A19–A0 (IF DRAM CYCLE, A22–A0 ARE TIME-MULTIPLEXED FOR RAS/CAS)
D15–D0
ClkOut
CASH, BHE
CASL, BLE
OE
WE
WAIT, SIZE16
XA–SCC
MIF
(MEMORY CONTROLLER)
Figure 4. Memory Bus Interface Signal Pins
Chip Selects and RAS pins
There are six chip select pins (CS5–CS0) mapped to six sets of
bank control registers. The following attributes are individually
programmable for each bank and associated chip select (or RAS if
DRAM): bank on/off, address range, external device access time,
detailed bus strobe sequence, DRAM cycle or generic bus cycle,
DRAM size if DRAM, and bus width. Pin CS0 is always generic in
order to service the boot device, thus CS0 cannot be connected to
DRAM.
WARNING
: On the external bus,
ALL
XA-SCC reads are 16 bit Reads. If the CPU instruction only specifies 8 bits, then the CPU uses
the appropriate byte, and discards the extra byte. Thus “8 Bit Reads” appear to be identical on the bus.
On an 8 bit bus, this will
appear as two consecutive 8 bit reads
even though the CPU instruction specified a byte read
Some 8 bit I/O devices (especially FIFOs) cannot operate correctly with 2 bytes being Read for a 1 Byte Read. The most common (and
least expensive) solution is to operate these 8 bit devices on a 16 bit bus, and access them in software on all odd byte (or all even byte)
boundaries. An added benefit of this technique is that byte reads are faster than on an 8 bit bus, because only 1 word is fetched (a single
read) instead of 2 consecutive bytes.
Clock Output
The CLKOUT pin allows easier external bus interfacing in some
situations. This output reflects the XTALIn clock input to the XA
(referred to internally as CClk or System Clock), but is delayed to
match the external bus outputs and strobes. The default is for
CLKOUT to be output enabled at reset, but it may be turned off
(tri-state disabled) by software via the MICFG MMR.
WARNING:
The capacitive loading on this output must not
exceed 40pf.
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