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| 型號： | PXB9202 |
| 英文描述： | ?Broadband Communication Controller |
| 中文描述： | ？寬帶通信控制器 |
| 文件頁數(shù)： | 1/2頁 |
| 文件大小： | 401K |
| 代理商： | PXB9202 |
P
R O D U C T
B
R I E F
N e v e r s t o p t h i n k i n g .
P
R E L I M I N A R Y
E a s y P o r t
Multi-Service Access Processor Family
PXB 9101/9102/9201/9202
Infineon’s EasyPort is a comprehensive broad-
band communication processor family. Based on
a powerful 64-bit MIPS CPU core sub-system, the
EasyPort features packet and ATM cell process-
ing functionality for data and voice/data Integrated
Access Devices (IADs), small and medium enter-
prise gateways, access routers, and Voice over IP
(VoIP) gateways. The EasyPort family supports
T1/E1 framers, standard xDSL transceivers, and
10BaseS
TM
Ethernet over VDSL technology. Easy-
Port has the compute power and architecture to
support firewalls and Virtual Private Networks
(VPN), as well as future applications and new con-
nectivity options such as Wireless LANs and
Bluetooth
TM
.
When used in combination with VINETIC
TM
, Infin-
eon's system solution supports VoATM and VoIP
on the same hardware platform, and supports up
to 32 compressed voice channels.
Using the EasyPort processor family, communi-
cation system vendors gain a powerful set of
tools enabling the transportation of data, video
and voice services integrated on the same hard-
ware and software platform.
Packet Processing
I
Embedded RISC coprocessor
I
Embedded data memory
I
Two 10/100 Mbit/s Ethernet
MAC controllers, one integrated
Ethernet PHY
I
USB 1.1 device controller
I
AAL5 (SAR) controller
I
DMA controller with a linked list
descriptor buffer
Voice Data Processing
I
Embedded RISC coprocessor
I
Two IOM-2/PCM interfaces
I
32 HDLC hardware accelerators
I
AAL2 (CPS) controller
I
Simple control of DuSLIC,
SICOFI and FALC
devices via a
Synchronous Serial Interface
(SSC)
ATM Cell Processing
I
ATM Layer controller
I
UTOPIA Level 1 and 2
I
Support for up to 128 VCCs
I
Traffic classes: CBR, VBR,
UBR+, GFR, UBR
I
Cell Buffer Manager with
integrated DMA controller for
up to 255 user cell queues
I
Queue specific traffic shaper in
hardware
I
Cell filtering
(2 filters; maskable VPI/VCI)
I
EPD, PPD congestion control
I
OAM according to ITU-T I.610
Embedded Processor Subsystem
I
200 MHz MIPS CPU core includ-
ing MMU with 32 dual entry TLB
I
External Bus Unit (50 MHz,
16-bit) for accessing system
memory (SRAM, Flash memory)
and external peripherals
I
Independent SDRAM I/F
(100 MHz, 32-bit, 256 MBytes)
Security Features
I
Security (VPN) and VoIP support
I
DES/3DES encryption/decryption
hardware accelerator
I
Throughput optimized dataflow
for VPN/IPsec processing
I
QoS optimized VoIP voice data
flow
Others
I
Power management
I
Lifeline service support
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