參數(shù)資料
型號(hào): PXA250
廠商: Intel Corp.
英文描述: Intel-R PXA250 and PXA210 Applications Processors
中文描述: 英特爾- R的PXA250和PXA210應(yīng)用處理器
文件頁(yè)數(shù): 37/46頁(yè)
文件大?。?/td> 431K
代理商: PXA250
Electrical, Mechanical, and Thermal Specification
PXA250 and PXA210
Datasheet
37
4.6.3
Watchdog Reset Timing
Watchdog Reset is an internally generated reset and therefore has no external pin dependencies.
The nRESETOUT pin is the only indicator of Watchdog Reset, and it stays asserted for t
DHW_OUT
.
Refer to Figure 5,
Hardware Reset Timing
on page 37.
4.6.4
GPIO Reset Timing
GPIO Reset is generated externally, and the source is reconfigured as a standard GPIO as soon as
the reset propagates internally. The clocks module is not reset by GPIO Reset, so the timing varies
based on the frequency of clock selected and if the Clocks and Power Manager is in the Frequency
Change Sequence when GPIO Reset is asserted (see Section 4.5.1,
32.768 kHz Oscillator
Specifications
on page 33.) Figure 6,
GPIO Reset Timing
on page 37 shows the possible timing
of GPIO Reset.
Figure 5. Hardware Reset Timing
Table 14. Hardware Reset Timing Specifications
Symbol
Description
Min
Typical
Max
Units
tDHW_NRESET
Minimum assertion time of nRESET
0.001
ms
tDHW_OUT_A
Delay between nRESET Asserted and
nRESET_OUT Asserted
0
0.001
ms
tDHW_OUT
Delay between nRESET deasserted and
nRESET_OUT deasserted
18.1
18.2
ms
nRESET
nRESET_OUT
t
DHW_NRESET
t
DHW_OUT
deasserted or the PXA250 applications processor enters Sleep Mode.
t
DHW_OUT_A
Note: nBATT_FAULT and nVDD_FAULT must be high before nRESET is
Figure 6. GPIO Reset Timing
GP[1]
nRESET_OUT
t
DHW_OUT
t
A_GP[1]
t
DHW_OUT_A
Note:
nBATT_FAULT and nVDD_FAULT must be high before nRESET is
deasserted or the application processor will enter Sleep Mode
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